LARTC - Oct 2006 - Need new way to improve SMP scalability for network router

Hi,
Currently I use dual cpu xeon server x86-64 with hp enabled
two intel Gbit Nics 82547
I have assigned every NIC irq to one phisical procesor but the two 
virtual procesors stay idle
and are not used for ether routeing or shaping
Is there a way to split work from two NICs on 4 CPUs ?

> Currently I use dual cpu xeon server x86-64 with hp enabled
> two intel Gbit Nics 82547
> I have assigned every NIC irq to one phisical procesor but the two 
> virtual procesors stay idle
> and are not used for ether routeing or shaping
> Is there a way to split work from two NICs on 4 CPUs ?
What do you expect to get? There are no 4 real CPUs. The only benefit
that the HT technology has is when you need very fast switching between
process/threads ... in this case the kernel should be prety good at it,
and won''t see any benefit from HT.

(I guess you are talking about HT.. you''ve said hp up there)


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> > and are not used for ether routeing or shaping
> > Is there a way to split work from two NICs on 4 CPUs ?
Put in two more nics and assign new interrupts to virtual processors.
It should work.
> What do you expect to get? There are no 4 real CPUs. The only benefit
> that the HT technology has is when you need very fast switching
> between process/threads ... in this case the kernel should be prety
> good at it, and won''t see any benefit from HT.
In fact you CAN use virtual processors made available by HT to assign
interrupts to them. This solution works well. I''ve seen P4-HT hauling
500.000 packets per second, with BGP and 70% utilisation.

cheers,
Marek Kierdelewicz