llvm dev - Jan 2017 - How parameter passing registers are used intelligently?

Hello LLVM Developers,

I need help to clear my understanding on register allocation.

For architecture like x86 LLVM does not add registers designated
for parameter passing to reserved registers.

For the function arguments
register allocation happens during ISel phase based on register usage
conventions.

Now for each virtual register there is one assigned register class for
when it is created.

So AllocationOrder class can provide as a hint register which could have
been
used for parameter passing. But register allocators should be able to use
them
when they are free i.e not used for conventional usage.

So how does LLVM register allocators take care of such situations?
Please also suggest the location of the code which is responsible for such
logic
if any.

Please correct my understanding if I am wrong.
Sincerely,
Vivek
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On 1/31/2017 5:19 AM, vivek pandya via llvm-dev wrote:
> So AllocationOrder class can provide as a hint register which could have
> been
> used for parameter passing. But register allocators should be able to
> use them
> when they are free i.e not used for conventional usage.
>
> So how does LLVM register allocators take care of such situations?
> Please also suggest the location of the code which is responsible for
> such logic
> if any.
The parameter registers are explicitly set/used in the code, and so they 
will be accounted for while calculating liveness information.  Register 
allocators use that information to make allocation decisions, and so 
they don't need to be explicitly aware of calling conventions.

-Krzysztof

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