Displaying 20 results from an estimated 27 matches for "allocationorder".
2017 Jan 31
1
How parameter passing registers are used intelligently?
...like x86 LLVM does not add registers designated
for parameter passing to reserved registers.
For the function arguments
register allocation happens during ISel phase based on register usage
conventions.
Now for each virtual register there is one assigned register class for
when it is created.
So AllocationOrder class can provide as a hint register which could have
been
used for parameter passing. But register allocators should be able to use
them
when they are free i.e not used for conventional usage.
So how does LLVM register allocators take care of such situations?
Please also suggest the location of t...
2020 May 29
2
Dynamically determine the CostPerUse value in the register allocator.
...t runtime for a kernel program.
Some initial thoughts on how to fix it:
1. Have a target interface (a switch) to enable/discard the CostPerUse value.
2. Get the register cost in the same way we define various calling conventions (*CallingConv.td).
3. Compute the CostPerUse in the way the AllocationOrder for the registers is determined during RA.
The first one is the easiest method and that solves the immediate problem we currently address.
However, the other two options are better if we want to associate different reg-cost values for different calling conventions (I presume, it will arise at some...
2012 Dec 01
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
...n function bar.
Loading/saving RBP should be managed by the stack frame setup/teardown code.
If it doesn't already, your allocator should filter out reserved registers
(See MachineRegisterInfo::isReserved(unsigned preg)) when assigning
physregs.
ArrayRef<MCPhysReg> pregs = TRC->getRawAllocationOrder(&MF);
for (int i = 0; i < pregs.size(); ++i) {
if (MRI->isReserved(pregs[i]))
continue;
// use preg...
}
You could also use the AllocationOrder class to simplify the task of
finding valid pregs, though it does require you to use VirtRegMap.
If you are already checking the reserv...
2012 Dec 03
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
...appropriate TargetRegisterClass (needed to call
> CreateSpillStackObject). Should I instead be generating code to save
> register EBP at the start of scinstal, restoring it at the end of that
> function?
>
> Susan
>
>
>
> ArrayRef<MCPhysReg> pregs = TRC->getRawAllocationOrder(&MF);
> for (int i = 0; i < pregs.size(); ++i) {
> if (MRI->isReserved(pregs[i]))
> continue;
> // use preg...
> }
>
> You could also use the AllocationOrder class to simplify the task of
> finding valid pregs, though it does require you to use VirtRegMap....
2020 May 30
2
Dynamically determine the CostPerUse value in the register allocator.
...me initial thoughts on how to fix it:
>
> 1. Have a target interface (a switch) to enable/discard the CostPerUse
> value.
> 2. Get the register cost in the same way we define various calling
> conventions (*CallingConv.td).
> 3. Compute the CostPerUse in the way the AllocationOrder for the
> registers is determined during RA.
>
>
>
> The first one is the easiest method and that solves the immediate problem
> we currently address.
>
> However, the other two options are better if we want to associate
> different reg-cost values for different callin...
2012 Dec 03
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...lass
> (needed to call CreateSpillStackObject). Should I instead be
> generating code to save register EBP at the start of scinstal,
> restoring it at the end of that function?
>
> Susan
>
>
>>
>> ArrayRef<MCPhysReg> pregs = TRC->getRawAllocationOrder(&MF);
>> for (int i = 0; i < pregs.size(); ++i) {
>> if (MRI->isReserved(pregs[i]))
>> continue;
>> // use preg...
>> }
>>
>> You could also use the AllocationOrder class to simplify the task
>> of finding...
2012 Nov 11
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
...r out any reserved registers). I've attached a test-case
> where I do this somewhat manually. In short:
>
> int regClass = MRI->getRegClass(vreg)->getID();
> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
> while (reservedRegs.test(*rItr))
> ++rItr;
> preg = *rItr;
>
> Alternatively, you could use the AllocationOrder class
> (lib/CodeGen/AllocationOrder.h). This has the benefit of considering
> register hin...
2012 Nov 08
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
...s an added
headache filter out any reserved registers). I've attached a test-case
where I do this somewhat manually. In short:
int regClass = MRI->getRegClass(vreg)->getID();
const TargetRegisterClass *trc = TRI->getRegClass(regClass);
ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
while (reservedRegs.test(*rItr))
++rItr;
preg = *rItr;
Alternatively, you could use the AllocationOrder class
(lib/CodeGen/AllocationOrder.h). This has the benefit of considering
register hints for improved coalescing too. It does,...
2012 Nov 11
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...9;ve attached a test-case where I do this
>> somewhat manually. In short:
>>
>> int regClass = MRI->getRegClass(vreg)->getID();
>> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
>> while (reservedRegs.test(*rItr))
>> ++rItr;
>> preg = *rItr;
>>
>> Alternatively, you could use the AllocationOrder class
>> (lib/CodeGen/AllocationOrder.h). Th...
2012 Nov 13
5
[LLVMdev] problem trying to write an LLVM register-allocation pass
...egisters). I've attached a test-case
>> where I do this somewhat manually. In short:
>>
>> int regClass = MRI->getRegClass(vreg)->getID();
>> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
>> while (reservedRegs.test(*rItr))
>> ++rItr;
>> preg = *rItr;
>>
>> Alternatively, you could use the AllocationOrder class
>> (lib/CodeGen/AllocationOrder.h). This has the benefit of c...
2012 Nov 09
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...r out any reserved registers). I've attached a
> test-case where I do this somewhat manually. In short:
>
> int regClass = MRI->getRegClass(vreg)->getID();
> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
> while (reservedRegs.test(*rItr))
> ++rItr;
> preg = *rItr;
>
> Alternatively, you could use the AllocationOrder class
> (lib/CodeGen/AllocationOrder.h). This has the benefit of considering
> register hi...
2012 Nov 13
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...test-case where I do this somewhat manually. In short:
>>>
>>> int regClass = MRI->getRegClass(vreg)->getID();
>>> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
>>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
>>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
>>> while (reservedRegs.test(*rItr))
>>> ++rItr;
>>> preg = *rItr;
>>>
>>> Alternatively, you could use the AllocationOrder class
>...
2012 Nov 14
1
[LLVMdev] problem trying to write an LLVM register-allocation pass
...manually. In
>>>> short:
>>>>
>>>> int regClass = MRI->getRegClass(vreg)->getID(**);
>>>> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
>>>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn)**;
>>>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
>>>> while (reservedRegs.test(*rItr))
>>>> ++rItr;
>>>> preg = *rItr;
>>>>
>>>> Alternatively, you could use the...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...eg47 in %vreg5
RHS = %vreg5 [464r,592B:0)[880B,992r:0) 0 at 464r
LHS = %vreg47 [400r,448B:0)[448B,464r:1)[1104r,1168B:2) 0 at 400r 1 at 448B-phi 2 at 1104r
merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B
erased:464r%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y %...
2012 Nov 07
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
Hi Susan,
Sorry for the delayed response. Thanks for the test cases - I'm looking in
to this now.
- Lang.
On Mon, Nov 5, 2012 at 2:58 PM, Susan Horwitz <horwitz at cs.wisc.edu> wrote:
> Hi Lang,
>
> I looked more into one of the problems I'm now having, and I've attached 3
> files:
>
> Gcra.cpp is like your version except that for two specific vregs it uses
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...r,592B:0)[880B,992r:0) 0 at 464r
> LHS = %vreg47 [400r,448B:0)[448B,464r:1)[1104r,1168B:2) 0 at 400r 1 at 448B-phi
> 2 at 1104r
> merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B
> erased:464r%vreg5<def> = COPY %vreg47<kill>;
> R600_Reg32:%vreg5,%vreg47
> AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W
> %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X
> %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y
> %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10...
2012 Nov 05
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
Hi Lang,
I looked more into one of the problems I'm now having, and I've attached
3 files:
Gcra.cpp is like your version except that for two specific vregs it uses
hard-coded pregs instead of the first in the corresponding class.
bug1.c is an input that causes the failed assertion for me. If I use
the non-debug version of LLVM-3.1 I instead get assembler errors like this:
Error:
2013 Mar 19
0
[LLVMdev] setCC and brcond
...%R2<imp-use>
# End machine code for function isZero.
********** DEBUG VARIABLES **********
********** Compute Spill Weights **********
********** Function: isZero
********** GREEDY REGISTER ALLOCATION **********
********** Function: isZero
selectOrSplit GPRegs:%vreg0 [16r,32r:0) 0 at 16r
AllocationOrder(GPRegs) = [ %R1 %R2 %R3 %R4 %R5 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R6 %R7 %R8 %R9 %R10 %R11 %R12 %R13 %R14 %R15 %R16 %R17 %R18 %R19 ]
assigning %vreg0 to %R2: R2
selectOrSplit GPRegs:%vreg4 [160r,176r:0) 0 at 160r
assigning %vreg4 to %R2: R2
selectOrSplit GPRegs:%vreg2 [112r,128r...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
352B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
368B tBX_RET 14, $noreg
# End machine code for function uECC_shared_secret.
selectOrSplit tGPR:%2 [16r,320r:0) 0 at 16r weight:5.738636e-03 w=5.738636e-03
AllocationOrder(tGPR) = [ $r0 $r1 $r2 $r3 $r4 $r5 $r6 ]
hints: $r2
Checking interference for %2 [16r,320r:0) 0 at 16r weight:5.738636e-03
$r2: IK_RegMask
$r0: IK_RegMask
$r1: IK_RegMask
$r3: IK_RegMask
$r4: IK_Free
missed hint $r2
assigning %2 to $r4: R4 [16r,320r:0) 0 at 16r
selectOrSplit tGPR:%1 [32r,304r:0)...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the