Hi
I write a machinefunction pass to print all the machinefunction's machine
instructions.
My target architecture is ARM. However, I don't understand some part of the
machine instructions.
Below is some of the assembly language for function A.
.text:0001C034 STMFD SP!,
{R4,R10,R11,LR}> .text:0001C038 ADD R11, SP, #8
> .text:0001C03C SUB SP, SP, #0x20
> .text:0001C040 STR R0, [R11,#statbuf]
> .text:0001C044 STR R1, [SP,#0x28+var_14]
> .text:0001C048 LDR R0, [SP,#0x28+var_14]
> .text:0001C04C LDR R0, [R0]
> .text:0001C050 STR R0, [SP,#0x28+ts]
> .text:0001C054 LDR R0, [SP,#0x28+ts]
> .text:0001C058 LDR R0, [R0,#4]
> .text:0001C05C CMN R0, #0xC0000002
> .text:0001C060 BNE loc_1C088
> .text:0001C064 B loc_1C068
>
>
Below is the corresponding MachineInstr
%1:gpr = COPY $r1>
> %0:gpr = COPY $r0
>
> %3:gpr = COPY %1:gpr
>
> %2:gpr = COPY %0:gpr
>
> STRi12 %0:gpr, %stack.1.statbuf.addr, 0, 14, $noreg :: (store 4 into
>> %ir.statbuf.addr)
>
> STRi12 %1:gpr, %stack.2.ts.addr, 0, 14, $noreg :: (store 4 into
>> %ir.ts.addr)
>
> %4:gpr = LDRi12 %stack.2.ts.addr, 0, 14, $noreg
>
> %5:gpr = LDRi12 killed %4:gpr, 0, 14, $noreg
>
> STRi12 killed %5:gpr, %stack.3.timespec, 0, 14, $noreg
>
> %6:gpr = LDRi12 %stack.3.timespec, 0, 14, $noreg
>
> %7:gpr = LDRi12 killed %6:gpr, 4, 14, $noreg
>
> CMNri killed %7:gpr, -1073741822, 14, $noreg
>
> Bcc %bb.3, 1, $cpsr
>
> B %bb.1
>
>
I don't know how "STMFD SP!, {R4,R10,R11,LR}" is translated into
the
machineinstr. Also, what does $noreg mean? what does gpr and the value in
front of it mean? It would be great if someone who are familiar with this
can explain it to me or give me some reference. Thank you very much.
Regards
Muhui
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That's a store-multiple that saves a few registers at the entry to the function. It's a part of the frame setup and it's generated during prolog/epilog insertion. The MIR code that you're showing is from before the frame creation, so it does not contain the instructions that do frame setup/cleanup. $noreg means "no register". It's used when an instruction required an operand that is a register, but none is specified. It's like a null-pointer but for registers. The instructions represented by MachineInstr do not have to match hardware instructions directly, many of them are instructions for compiler's internal use, so you can see things that don't match the final assembly. -Krzysztof On 6/15/2018 11:28 AM, Muhui Jiang via llvm-dev wrote:> Hi > > I write a machinefunction pass to print all the machinefunction's > machine instructions. > > My target architecture is ARM. However, I don't understand some part of > the machine instructions. > > Below is some of the assembly language for function A. > > .text:0001C034 STMFD SP!, {R4,R10,R11,LR} > .text:0001C038 ADD R11, SP, #8 > .text:0001C03C SUB SP, SP, #0x20 > .text:0001C040 STR R0, [R11,#statbuf] > .text:0001C044 STR R1, [SP,#0x28+var_14] > .text:0001C048 LDR R0, [SP,#0x28+var_14] > .text:0001C04C LDR R0, [R0] > .text:0001C050 STR R0, [SP,#0x28+ts] > .text:0001C054 LDR R0, [SP,#0x28+ts] > .text:0001C058 LDR R0, [R0,#4] > .text:0001C05C CMN R0, #0xC0000002 > .text:0001C060 BNE loc_1C088 > .text:0001C064 B loc_1C068 > > > Below is the corresponding MachineInstr > > %1:gpr = COPY $r1 > > %0:gpr = COPY $r0 > > %3:gpr = COPY %1:gpr > > %2:gpr = COPY %0:gpr > > STRi12 %0:gpr, %stack.1.statbuf.addr, 0, 14, $noreg :: (store 4 > into %ir.statbuf.addr) > > STRi12 %1:gpr, %stack.2.ts.addr, 0, 14, $noreg :: (store 4 into > %ir.ts.addr) > > %4:gpr = LDRi12 %stack.2.ts.addr, 0, 14, $noreg > > %5:gpr = LDRi12 killed %4:gpr, 0, 14, $noreg > > STRi12 killed %5:gpr, %stack.3.timespec, 0, 14, $noreg > > %6:gpr = LDRi12 %stack.3.timespec, 0, 14, $noreg > > %7:gpr = LDRi12 killed %6:gpr, 4, 14, $noreg > > CMNri killed %7:gpr, -1073741822, 14, $noreg > > Bcc %bb.3, 1, $cpsr > > B %bb.1 > > > I don't know how "STMFD SP!, {R4,R10,R11,LR}" is translated into the > machineinstr. Also, what does $noreg mean? what does gpr and the value > in front of it mean? It would be great if someone who are familiar with > this can explain it to me or give me some reference. Thank you very much. > > Regards > Muhui > > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Hi Krzysztof Thank you very much for your quick and clear reply. I know that MIR may not match hardware instructions directly. However, I think the semantics should be similar. For example, the first instruction is a store-multiple instruction in ARM. I think the first four MIR I shown should have the similar semantics with the first three hardware instructions. I still cannot see the relationships between them. Also, what does gpr mean.. Do I lost some information? Thank you so much if you can explain it in a little bit detail. Regards Muhui 2018-06-15 12:33 GMT-04:00 Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org>:> That's a store-multiple that saves a few registers at the entry to the > function. It's a part of the frame setup and it's generated during > prolog/epilog insertion. > > The MIR code that you're showing is from before the frame creation, so it > does not contain the instructions that do frame setup/cleanup. > > $noreg means "no register". It's used when an instruction required an > operand that is a register, but none is specified. It's like a null-pointer > but for registers. The instructions represented by MachineInstr do not have > to match hardware instructions directly, many of them are instructions for > compiler's internal use, so you can see things that don't match the final > assembly. > > -Krzysztof > > > > On 6/15/2018 11:28 AM, Muhui Jiang via llvm-dev wrote: > >> Hi >> >> I write a machinefunction pass to print all the machinefunction's >> machine instructions. >> >> My target architecture is ARM. However, I don't understand some part of >> the machine instructions. >> >> Below is some of the assembly language for function A. >> >> .text:0001C034 STMFD SP!, {R4,R10,R11,LR} >> .text:0001C038 ADD R11, SP, #8 >> .text:0001C03C SUB SP, SP, #0x20 >> .text:0001C040 STR R0, [R11,#statbuf] >> .text:0001C044 STR R1, [SP,#0x28+var_14] >> .text:0001C048 LDR R0, [SP,#0x28+var_14] >> .text:0001C04C LDR R0, [R0] >> .text:0001C050 STR R0, [SP,#0x28+ts] >> .text:0001C054 LDR R0, [SP,#0x28+ts] >> .text:0001C058 LDR R0, [R0,#4] >> .text:0001C05C CMN R0, #0xC0000002 >> .text:0001C060 BNE loc_1C088 >> .text:0001C064 B loc_1C068 >> >> >> Below is the corresponding MachineInstr >> >> %1:gpr = COPY $r1 >> >> %0:gpr = COPY $r0 >> >> %3:gpr = COPY %1:gpr >> >> %2:gpr = COPY %0:gpr >> >> STRi12 %0:gpr, %stack.1.statbuf.addr, 0, 14, $noreg :: (store 4 >> into %ir.statbuf.addr) >> >> STRi12 %1:gpr, %stack.2.ts.addr, 0, 14, $noreg :: (store 4 into >> %ir.ts.addr) >> >> %4:gpr = LDRi12 %stack.2.ts.addr, 0, 14, $noreg >> >> %5:gpr = LDRi12 killed %4:gpr, 0, 14, $noreg >> >> STRi12 killed %5:gpr, %stack.3.timespec, 0, 14, $noreg >> >> %6:gpr = LDRi12 %stack.3.timespec, 0, 14, $noreg >> >> %7:gpr = LDRi12 killed %6:gpr, 4, 14, $noreg >> >> CMNri killed %7:gpr, -1073741822, 14, $noreg >> >> Bcc %bb.3, 1, $cpsr >> >> B %bb.1 >> >> >> I don't know how "STMFD SP!, {R4,R10,R11,LR}" is translated into the >> machineinstr. Also, what does $noreg mean? what does gpr and the value in >> front of it mean? It would be great if someone who are familiar with this >> can explain it to me or give me some reference. Thank you very much. >> >> Regards >> Muhui >> >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >> > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180615/c773b379/attachment.html>