search for: ldri12

...ze=4, align=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJ...

...0:gpr = COPY $r0 > > %3:gpr = COPY %1:gpr > > %2:gpr = COPY %0:gpr > > STRi12 %0:gpr, %stack.1.statbuf.addr, 0, 14, $noreg :: (store 4 into >> %ir.statbuf.addr) > > STRi12 %1:gpr, %stack.2.ts.addr, 0, 14, $noreg :: (store 4 into >> %ir.ts.addr) > > %4:gpr = LDRi12 %stack.2.ts.addr, 0, 14, $noreg > > %5:gpr = LDRi12 killed %4:gpr, 0, 14, $noreg > > STRi12 killed %5:gpr, %stack.3.timespec, 0, 14, $noreg > > %6:gpr = LDRi12 %stack.3.timespec, 0, 14, $noreg > > %7:gpr = LDRi12 killed %6:gpr, 4, 14, $noreg > > CMNri killed %7:gpr, -1...

...= COPY %0:gpr >> >> STRi12 %0:gpr, %stack.1.statbuf.addr, 0, 14, $noreg :: (store 4 >> into %ir.statbuf.addr) >> >> STRi12 %1:gpr, %stack.2.ts.addr, 0, 14, $noreg :: (store 4 into >> %ir.ts.addr) >> >> %4:gpr = LDRi12 %stack.2.ts.addr, 0, 14, $noreg >> >> %5:gpr = LDRi12 killed %4:gpr, 0, 14, $noreg >> >> STRi12 killed %5:gpr, %stack.3.timespec, 0, 14, $noreg >> >> %6:gpr = LDRi12 %stack.3.timespec, 0, 14, $noreg >> >> %7:gpr = LDRi1...

...n=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc =...

...n=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc =...

...ze=4, align=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJ...

...here any plan to update the code analysis to distinguish virtual register's sub-registers definitions? So that GPRPair sub-registers can be used by instructions that do not return 64 bit value? Example: This is a simple example of machine instructions I caused to be generated. I forced the LDRi12 instructions to use a GPRPair sub-register. The copy into %vreg4 asserts because of the two definitions of vreg9, coming from vreg9:gsub_0 and vreg9:gsub_1. %vreg1<def> = COPY %R1; GPR:%vreg1 %vreg2<def> = MOVi32imm <ga:@a>; GPR:%vreg2 %vreg3<def...

...t;int") # preds left : 1 # succs left : 2 # rdefs left : 0 Latency : 1 Depth : 2 Height : 0 Predecessors: val SU(1): Latency=1 Reg=%R2 Successors: antiSU(3): Latency=0 ch SU(3): Latency=0 SU(3): %R0<def> = LDRi12 %R1<kill>, 0, pred:14, pred:%noreg; mem:Volatile LD4[%p2](tbaa=!"int") # preds left : 2 # succs left : 1 # rdefs left : 0 Latency : 1 Depth : 2 Height : 0 Predecessors: antiSU(2): Latency=0 ch SU(2): Latency=...

...gt; wrote: > Sorta. getBinaryCodeForInst() is auto-generated by tablegen, so shouldn't be modified directly. The target can register hooks for instruction operands for any special encoding needs, including registering fixups, using the EncoderMethod string. For an example, have a look at the LDRi12 instruction and how it registers a fixup for the addrmode_imm12 operand when it needs one. Hi Jim,. follow up question for ya: The current movt/movw pair (as defined in ARMInstrInfo.td) does not use EncoderMethod string to declare a special case handler. At the current time, for the assembly p...

...a pattern I specified: First, here is a snippet of a successful match (done in ARM mode) ISEL: Starting pattern match on root node: 0x1e7adf0: i32,ch = load 0x1e4c030, 0x1e78210, 0x1e78310<LD4[ConstantPool]> [ID=10] Initial Opcode index to 24435 ...... Morphed node: 0x1e7adf0: i32,ch = LDRi12 0x1e78210, 0x1e78010, 0x1e7aef0, 0x1e7b0f0, 0x1e4c030<Mem:LD4[ConstantPool]> ISEL: Match complete! ISEL: Starting pattern match on root node: 0x1e78210: i32 = ARMISD::Wrapper 0x1e77f10 [ID=9] Initial Opcode index to 49796 OpcodeSwitch from 49799 to 49891 Skipped scope entry (due to fa...