Displaying 14 results from an estimated 14 matches for "stri12".
2018 Apr 09
2
How to get the case value from Machine Instruction
...Objects:
fi#0: size=1, align=0, at location [SP]
fi#1: size=4, align=4, at location [SP+8]
fi#2: size=4, align=4, at location [SP+4]
fi#3: size=4, align=4, at location [SP]
Jump Tables:
%jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5
%bb.0: derived from LLVM BB %0
%r0 = MOVi 0, 14, %noreg, %noreg
STRi12 %r0, %stack.1, 14, %noreg
%r0 = MOVi 4, 14, %noreg, %noreg
STRi12 %r0, %stack.2, 14, %noreg
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = SUBri %r0, 1, 14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %cpsr
STRi12 %r0, %stack.3, 14, %noreg
Bcc %bb.6, 8, %cpsr
Successors according to CFG: %bb...
2018 Apr 09
0
How to get the case value from Machine Instruction
...fi#0: size=1, align=0, at location [SP]
fi#1: size=4, align=4, at location [SP+8]
fi#2: size=4, align=4, at location [SP+4]
fi#3: size=4, align=4, at location [SP]
Jump Tables:
%jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5
%bb.0: derived from LLVM BB %0
%r0 = MOVi 0, 14, %noreg, %noreg
STRi12 %r0, %stack.1, 14, %noreg
%r0 = MOVi 4, 14, %noreg, %noreg
STRi12 %r0, %stack.2, 14, %noreg
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = SUBri %r0, 1, 14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %cpsr
STRi12 %r0, %stack.3, 14, %noreg
Bcc %bb.6, 8, %cpsr
Successors according to...
2018 Apr 10
1
How to get the case value from Machine Instruction
...fi#0: size=1, align=0, at location [SP]
fi#1: size=4, align=4, at location [SP+8]
fi#2: size=4, align=4, at location [SP+4]
fi#3: size=4, align=4, at location [SP]
Jump Tables:
%jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5
%bb.0: derived from LLVM BB %0
%r0 = MOVi 0, 14, %noreg, %noreg
STRi12 %r0, %stack.1, 14, %noreg
%r0 = MOVi 4, 14, %noreg, %noreg
STRi12 %r0, %stack.2, 14, %noreg
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = SUBri %r0, 1, 14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %cpsr
STRi12 %r0, %stack.3, 14, %noreg
Bcc %bb.6, 8, %cpsr
Successors according to...
2018 Apr 09
0
How to get the case value from Machine Instruction
...Objects:
fi#0: size=1, align=0, at location [SP]
fi#1: size=4, align=4, at location [SP+8]
fi#2: size=4, align=4, at location [SP+4]
fi#3: size=4, align=4, at location [SP]
Jump Tables:
%jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5
%bb.0: derived from LLVM BB %0
%r0 = MOVi 0, 14, %noreg, %noreg
STRi12 %r0, %stack.1, 14, %noreg
%r0 = MOVi 4, 14, %noreg, %noreg
STRi12 %r0, %stack.2, 14, %noreg
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = SUBri %r0, 1, 14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %cpsr
STRi12 %r0, %stack.3, 14, %noreg
Bcc %bb.6, 8, %cpsr
Successors according to CFG: %bb...
2018 Jun 15
2
Strange Machineinstr
...MN R0, #0xC0000002
> .text:0001C060 BNE loc_1C088
> .text:0001C064 B loc_1C068
>
>
Below is the corresponding MachineInstr
%1:gpr = COPY $r1
>
> %0:gpr = COPY $r0
>
> %3:gpr = COPY %1:gpr
>
> %2:gpr = COPY %0:gpr
>
> STRi12 %0:gpr, %stack.1.statbuf.addr, 0, 14, $noreg :: (store 4 into
>> %ir.statbuf.addr)
>
> STRi12 %1:gpr, %stack.2.ts.addr, 0, 14, $noreg :: (store 4 into
>> %ir.ts.addr)
>
> %4:gpr = LDRi12 %stack.2.ts.addr, 0, 14, $noreg
>
> %5:gpr = LDRi12 killed %4:gpr, 0, 14, $noreg
&...
2018 Jun 15
3
Strange Machineinstr
...B loc_1C068
>>
>>
>> Below is the corresponding MachineInstr
>>
>> %1:gpr = COPY $r1
>>
>> %0:gpr = COPY $r0
>>
>> %3:gpr = COPY %1:gpr
>>
>> %2:gpr = COPY %0:gpr
>>
>> STRi12 %0:gpr, %stack.1.statbuf.addr, 0, 14, $noreg :: (store 4
>> into %ir.statbuf.addr)
>>
>> STRi12 %1:gpr, %stack.2.ts.addr, 0, 14, $noreg :: (store 4 into
>> %ir.ts.addr)
>>
>> %4:gpr = LDRi12 %stack.2.ts.addr, 0, 14, $noreg
>>...
2012 Feb 04
4
[LLVMdev] ARMLoadStoreOptimizer bug
...to come up with a minimal example; it is breaking
in our stage 2 LLVM build.
But here's what I'm seeing in the debug output:
# Before ARMLoadStoreOptimizer:
BB#21: derived from LLVM BB %cond.end
Live Ins: %LR %R0 %R1 %R7 %R10 %R11
Predecessors according to CFG: BB#14 BB#18
STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg;
mem:ST4[%first257](tbaa=!"int")
%R1<def> = ADDri %R1<kill>, 4, pred:14, pred:%noreg, opt:%CPSR<def>
Bcc <BB#23>, pred:0, pred:%CPSR<kill>
B <BB#22>
Successors according to CFG: B...
2012 Feb 07
0
[LLVMdev] ARMLoadStoreOptimizer bug
...breaking in our stage 2 LLVM build.
>
> But here's what I'm seeing in the debug output:
>
> # Before ARMLoadStoreOptimizer:
> BB#21: derived from LLVM BB %cond.end
> Live Ins: %LR %R0 %R1 %R7 %R10 %R11
> Predecessors according to CFG: BB#14 BB#18
> STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg; mem:ST4[%first257](tbaa=!"int")
> %R1<def> = ADDri %R1<kill>, 4, pred:14, pred:%noreg, opt:%CPSR<def>
> Bcc <BB#23>, pred:0, pred:%CPSR<kill>
> B <BB#22>
> Successors...
2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
...i 0, pred:14, pred:%noreg, opt:%noreg
> TSTri %R3<kill>, 255, pred:14, pred:%noreg, %CPSR<imp-def>;
> Bcc <BB#9>, pred:0, pred:%CPSR<kill>;
>
> BB#8:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRi12 %R6, %R7<kill>, 4, pred:14, pred:%noreg; mem:ST4[%__size_.i3.i.i.i.i]
> %R6<def> = LDRrs %R4, %R6<kill>, 16386, pred:14, pred:%noreg; mem:LD4[%0]
> BX %R6<kill>
>
> BB#9:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors accord...
2012 Feb 07
1
[LLVMdev] ARMLoadStoreOptimizer bug
...gt; >
> > But here's what I'm seeing in the debug output:
> >
> > # Before ARMLoadStoreOptimizer:
> > BB#21: derived from LLVM BB %cond.end
> > Live Ins: %LR %R0 %R1 %R7 %R10 %R11
> > Predecessors according to CFG: BB#14 BB#18
> > STRi12 %R7<kill>, %R1, 0, pred:14, pred:%noreg;
> mem:ST4[%first257](tbaa=!"int")
> > %R1<def> = ADDri %R1<kill>, 4, pred:14, pred:%noreg,
> opt:%CPSR<def>
> > Bcc <BB#23>, pred:0, pred:%CPSR<kill>
> > B <BB#2...
2012 Jun 12
2
[LLVMdev] Latency of true depency of store followed by aliased load in ScheduleDAGInstrs
...pendency of a
store followed by an aliased load in ScheduleDAGInstrs. The latency
seems to depend on the store and load being volatile or not as can be
seen in the post-RA-sched debug output of the attached ARM example:
$ llc -O3 -debug-only=post-RA-sched store_load_latency_test.ll
...
SU(2): STRi12 %R2<kill>, %R0<kill>, 0, pred:14, pred:%noreg; mem:Volatile ST4[%p1](tbaa=!"int")
# preds left : 1
# succs left : 2
# rdefs left : 0
Latency : 1
Depth : 2
Height : 0
Predecessors:
val SU(1): Latency=1 Reg=%...
2014 Jul 23
2
[LLVMdev] JIT on armhf, again
On 7/23/14, 1:20 PM, Tim Northover wrote:
[...]
> You should probably be specifying a triple directly, and making it an
> AAPCS-VFP one for good measure: "armv7-linux-gnueabihf" for example,
> or "thumbv7-none-eabihf". You shouldn't even need to set FloatABI for
> those two.
How do I do this? (I can't find any examples, and the API is decidedly
unclear...)
2017 Oct 11
2
{ARM} IfConversion does not detect BX instruction as a branch
...d:%noreg, opt:%noreg
> TSTri %R3<kill>, 255, pred:14, pred:%noreg, %CPSR<imp-def>;
> Bcc <BB#9>, pred:0, pred:%CPSR<kill>;
>
>
> BB#8:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRi12 %R6, %R7<kill>, 4, pred:14, pred:%noreg;
> mem:ST4[%__size_.i3.i.i.i.i]
> %R6<def> = LDRrs %R4, %R6<kill>, 16386, pred:14, pred:%noreg;
> mem:LD4[%0]
> BX %R6<kill>
>
> BB#9:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
>...
2014 Jul 23
2
[LLVMdev] JIT on armhf, again
...working --- hardfloat code is now being generated,
and it even seems to be right most of the time!
Unfortunately it looks like it's getting calling conventions wrong. This
IR code:
define void @Entrypoint(float %in, float* %out) {
store float %in, float* %out
}
...gets compiled to this:
STRi12 %R0<kill>, %R1<kill>, 0, pred:14, pred:%noreg; mem:ST4[%out]
BX_RET pred:14, pred:%noreg
(typed by hand, so may contain typos).
So it looks like it's assuming that float parameters are being passed in
integer registers, which isn't the case on armhf.
Could it be under the i...