search for: noreg

...at that point? I've found a failing testcase where register scavenging complains about redefining a live register. The (ARM) code looks like this: bb408: 0x9b07468, LLVM BB @0x9ae9010, ID#8: Live Ins: %r4 %r5 %r7 Predecessors according to CFG: 0x9b08398 (#71) STR %r4<kill>, %sp, %NOREG, 0, 14, %NOREG %r4 = MOVi 0, 14, %NOREG, %NOREG %r0 = MOVr %r7<kill>, 14, %NOREG, %NOREG %r1 = MOVr %r5<kill>, 14, %NOREG, %NOREG %r2 = LDR <fi#1>, %NOREG, 0, 14, %NOREG %r3 = MOVr %r4, 14, %NOREG, %NOREG BL <ga:gimplify_cond_expr>, %r0<kill>, %r1<kill>, %r...

...prevent this? Thanks, -Peng ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1 %vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2 MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3 %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112 %vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111] GR32:%vreg189,%vreg112 %vreg190&l...

...DOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1 > %vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2 > MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3 > %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112 > %vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111] GR32:%vreg189,%vreg112...

...ollows: Frame Objects: fi#0: size=1, align=0, at location [SP] fi#1: size=4, align=4, at location [SP+8] fi#2: size=4, align=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors accord...

...neInstr *plop = BuildMI(MF, DebugLoc(),tii.get(X86::JMP_4)).addMBB(origBB.at(1)); newEntry->push_back(plop); return false; } And here is the resulting code (it's a simple program with some 'if'): (null) BB#4 JMP_4 <BB#0> if.end BB#3 %RDI<def> = LEA64r %RIP, 1, %noreg, <ga:@.str2>, %noreg ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> %AL<def> = MOV8ri 0 CALL64pcrel32 <ga:@printf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use,kill>, %EAX<imp-def> ADJCALLSTACKUP64...

...rame Objects: fi#0: size=1, align=0, at location [SP] fi#1: size=4, align=4, at location [SP+8] fi#2: size=4, align=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successo...

...rame Objects: fi#0: size=1, align=0, at location [SP] fi#1: size=4, align=4, at location [SP+8] fi#2: size=4, align=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successo...

...ollows: Frame Objects: fi#0: size=1, align=0, at location [SP] fi#1: size=4, align=4, at location [SP+8] fi#2: size=4, align=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors accord...

...), [val] "r" (val) : "memory"); } ------------------------ # *** IR Dump Before Post RA top-down list latency scheduler ***: BB#6: derived from LLVM BB %if.else Live Ins: %LR %R2 %R3 %R4 %R7 %R12 Predecessors according to CFG: BB#0 CMPri %R12, 1, pred:14, pred:%noreg, %CPSR<imp-def> <<<<<<<<<<< First comparison using lock_flag ; R12 holds lock_flag %R5<def> = IMPLICIT_DEF Bcc <BB#21>, pred:1, pred:%CPSR<kill> <<<<<<<<<<< Successors according to CFG: BB#...

...%call } Which is probably the best representation to have at this relatively high level. At the machine level it looks like it is the register coalescer that is duplicating the constant. It transforms 0B BB#0: derived from LLVM BB %entry 16B %vreg0<def> = MOV64rm %RIP, 1, %noreg, <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg1 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0; mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0 64B...

For the little C test program where a constant is stored in memory and also used as a parameter: #include <stdint.h> uint64_t val, *p; extern uint64_t xtr( uint64_t); uint64_t caller() { uint64_t x; p = &val; x = 12345123400L; *p = x; return xtr(x); } clang (3.2, 3.3 and svn) generates the following X86 code (at -O3): caller: movq

...e IfConvertion MachinePass. Here's is what it looks like before and after. > #BEFORE IfConversion MachinePass > > BB#7: > Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12 > Predecessors according to CFG: BB#5 BB#6 > STRBi12 %R5, %R6<kill>, 0, pred:14, pred:%noreg; mem:ST1[%cond.i23.i.i.i] > %R6<def> = LDRBi12 %R7, 0, pred:14, pred:%noreg; mem:LD1[%15](align=4) > %R3<def> = EORri %R6, 254, pred:14, pred:%noreg, opt:%noreg > %R3<def> = ANDrr %R3<kill>, %R6<kill>, pred:14, pred:%noreg, opt:%noreg > %R6<def> = M...

...best representation to have at this relatively high level. > > At the machine level it looks like it is the register coalescer that > is duplicating the constant. It transforms > > 0B BB#0: derived from LLVM BB %entry > 16B %vreg0<def> = MOV64rm %RIP, 1, %noreg, > <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0 > 32B %vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5], > %noreg; mem:LD8[GOT] GR64:%vreg1 > 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0; > mem:ST8[@p](tbaa=!"any pointer&quot...

...; <bool>:7 [#uses=1] br bool %7, label %entry.bb19_crit_edge.i270, label %bb.preheader.i271 It gets converted to the following MachineBasicBlock __exp.exit (0x8c58628, LLVM BB @0x8c1c558, ID#21): Predecessors according to CFG: 0x8c53a90 0x8c55b50 MOV32mi %EBP, 1, %NOREG, -224, <ga:DataStore> %EAX = MOV32rm %EBP, 1, %NOREG, -224 %EAX = ADD32ri8 %EAX, 40 MOV32mi %EAX, 1, %NOREG, 0, 0 MOV32mi %EAX, 1, %NOREG, 4, 1075576832 %ESP = SUB32ri %ESP, 16 %XMM0 = CVTSI2SDrr %EDI MOVSDmr %ESP, 1, %NOREG, 0, %XMM0...

...restrictive. For example, here is a case where it succeeds: 8944B BB#53: derived from LLVM BB %172 Live Ins: %R4 %R6 %D8 %Q5 %R9 %R7 %R8 %R10 %R5 %R11 Predecessors according to CFG: BB#52 8976B %R1<def> = t2LEApcrelJT <jt#2>, 2, pred:14, pred:%noreg 8992B %R1<def> = t2ADDrs %R1<kill>, %R10, 18, pred:14, pred:%noreg, opt:%noreg 9004B %LR<def> = t2MOVi 1, pred:14, pred:%noreg, opt:%noreg 9008B t2BR_JT %R1<kill>, %R10<kill>, <jt#2>, 2 Shrink JT: t2BR_JT %R1<kill>, %R10...

...***: # Machine code for function CGA_kernel_read: Post SSA Function Live Ins: %P0 in %vreg5, %P1 in %vreg6 Function Live Outs: %P15 0B BB#0: derived from LLVM BB %entry Live Ins: %P0 %P1 16B %vreg6<def> = COPY %P1; IntRegs:%vreg6 48B %vreg8<def> = MOV32ri <ga:@fifo>, pred:%noreg; IntRegs:%vreg8 dbg:../src/getbits.c:46:1 64B %vreg9<def> = LDUBri %vreg8, 1, pred:%noreg; mem:LD1[getelementptr inbounds (%struct.FIFO* @fifo, i32 0, i32 1)] IntRegs:%vreg9,%vreg8 dbg:../src/getbits.c:46:1 80B %vreg10<def> = CMPEQI %vreg9<kill>, 0, pred:%noreg; PredRegs:%vreg10...

...BNE loc_1C088 > .text:0001C064 B loc_1C068 > > Below is the corresponding MachineInstr %1:gpr = COPY $r1 > > %0:gpr = COPY $r0 > > %3:gpr = COPY %1:gpr > > %2:gpr = COPY %0:gpr > > STRi12 %0:gpr, %stack.1.statbuf.addr, 0, 14, $noreg :: (store 4 into >> %ir.statbuf.addr) > > STRi12 %1:gpr, %stack.2.ts.addr, 0, 14, $noreg :: (store 4 into >> %ir.ts.addr) > > %4:gpr = LDRi12 %stack.2.ts.addr, 0, 14, $noreg > > %5:gpr = LDRi12 killed %4:gpr, 0, 14, $noreg > > STRi12 killed %5:gpr, %stack.3.times...

...rs at the entry to the > function. It's a part of the frame setup and it's generated during > prolog/epilog insertion. > > The MIR code that you're showing is from before the frame creation, so it > does not contain the instructions that do frame setup/cleanup. > > $noreg means "no register". It's used when an instruction required an > operand that is a register, but none is specified. It's like a null-pointer > but for registers. The instructions represented by MachineInstr do not have > to match hardware instructions directly, many of th...

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

...> > ** ** > > 8944B BB#53: derived from LLVM BB %172**** > > Live Ins: %R4 %R6 %D8 %Q5 %R9 %R7 %R8 %R10 %R5 %R11**** > > Predecessors according to CFG: BB#52**** > > 8976B %R1<def> = t2LEApcrelJT <jt#2>, 2, pred:14, pred:%noreg*** > * > > 8992B %R1<def> = t2ADDrs %R1<kill>, %R10, 18, pred:14, > pred:%noreg, opt:%noreg**** > > 9004B %LR<def> = t2MOVi 1, pred:14, pred:%noreg, opt:%noreg**** > > 9008B t2BR_JT %R1<kill>, %R10<kill>, <jt#2&g...