llvm dev - Nov 2013 - [LLVMdev] [PATCH] Detect Haswell subarchitecture (i.e. using -march=native)

> I promise I'll do the review of your code after that.
Tim, I don’t want to push too much. But since there’s 3.4 release on the
horizon, maybe you could find a moment review this patch. Especially Haswell is
all there since few months.

Cheers,
-- 
Adam

---
 lib/Support/Host.cpp            | 8 ++++++++
 lib/Target/X86/X86Subtarget.cpp | 3 ++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp
index 380df6b..2235456 100644
--- a/lib/Support/Host.cpp
+++ b/lib/Support/Host.cpp
@@ -138,6 +138,8 @@ std::string sys::getHostCPUName() {
   // switch, then we have full AVX support.
   const unsigned AVXBits = (1 << 27) | (1 << 28);
   bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
+  bool HasAVX2 = HasAVX && !GetX86CpuIDAndInfo(0x7, &EAX, &EBX,
&ECX, &EDX) &&
+                 (EBX & 0x20);
   GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
   bool Em64T = (EDX >> 29) & 0x1;
 
@@ -258,6 +260,12 @@ std::string sys::getHostCPUName() {
         // versions instead of the i7 versions).
         return HasAVX ? "core-avx-i" : "corei7";
 
+      // Haswell:
+      case 60:
+        // Not all Haswell processors support AVX too (such as the Pentium
+        // versions instead of the i7 versions).
+        return HasAVX2 ? "core-avx2" : "corei7";
+
       case 28: // Most 45 nm Intel Atom processors
       case 38: // 45 nm Atom Lincroft
       case 39: // 32 nm Atom Medfield
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index fa04c38..d221316 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -285,7 +285,8 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
          (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
          (Family == 6 && Model == 0x2A) || // SandyBridge
          (Family == 6 && Model == 0x2D) || // SandyBridge:
SandyBridge-E*
-         (Family == 6 && Model == 0x3A))) {// IvyBridge
+         (Family == 6 && Model == 0x3A) || // IvyBridge
+         (Family == 6 && Model == 0x3C))) {// Haswell
       IsUAMemFast = true;
       ToggleFeature(X86::FeatureFastUAMem);
     }
-- 
1.8.3.4 (Apple Git-47)

Hi Adam,
> +  bool HasAVX2 = HasAVX && !GetX86CpuIDAndInfo(0x7, &EAX,
&EBX, &ECX, &EDX) &&
> +                 (EBX & 0x20);
I don't think this guarantees %ecx is 0, does it? Wasn't that the
entire reason the original code went wrong?

Cheers.

Tim.

>> +  bool HasAVX2 = HasAVX && !GetX86CpuIDAndInfo(0x7, &EAX,
&EBX, &ECX, &EDX) &&
>> +                 (EBX & 0x20);
> 
> I don't think this guarantees %ecx is 0, does it? Wasn't that the
> entire reason the original code went wrong?
I don’t remember really, but presuming the conclusions of the discussion, seems
it is fixed now. It was something about registers when using inline assembly.
Anyway this works just fine on all my Haswell machines.

Regards,
-- 
Adam