search for: haswel

I have one of those new little NUC's and installed Centos 7.1 on it. lspci shows 00:00.0 Host bridge: Intel Corporation Haswell-ULT DRAM Controller (rev 09) 00:02.0 VGA compatible controller: Intel Corporation Haswell-ULT Integrated Graphics Controller (rev 09) 00:03.0 Audio device: Intel Corporation Haswell-ULT HD Audio Controller (rev 09) 00:14.0 USB controller: Intel Corporation 8 Series USB xHCI HC (rev 04) 00:16.0 Com...

Hello, This is my first patch on this list, however I've already submitted several trough bug tracking system. Since it probably needs some review and it's not a bug I am submitting it here. The main intent of this patch is to detect "core-avx2" platform on Haswell i7 CPUs when running -march=native. Currently it detects it as generic x86_64. lib/Support/Host.cpp: * Haswell is detected for CPUID Family 6 Model 60 * Similar to Ivy and Sandy Bridge we check for AVX2 since some Haswell Pentiums are SSE4.x only * I have marked HasAVX2 as "volatile", s...

> I promise I'll do the review of your code after that. Tim, I don’t want to push too much. But since there’s 3.4 release on the horizon, maybe you could find a moment review this patch. Especially Haswell is all there since few months. Cheers, -- Adam --- lib/Support/Host.cpp | 8 ++++++++ lib/Target/X86/X86Subtarget.cpp | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index 380df6b..2235456 100644 --- a/lib/Support/H...

...omments . I tried now with force options for CPU flag which were not supported . Now the command with non fully supported CPU model gets executed , But i am surprised to see that still Guest cpu model is not changed and still same as host cpu model(SAndy Bridge) Why don't i see the model as HAswell now , could you please comment. Command used : virt-install --virt-type kvm --name controller-0 --cpu Haswell-noTSX,+fma,+movbe,+fsgsbase,+bmi1,+avx2,+smep,+bmi2,+erms,+invpcid --ram=8120 --vcpus=4,sockets=1 Linux process for KVM : 7479 1 37 10:13 ? 01:13:21 /usr/libexec/qemu-kvm -...

...is guarantees %ecx is 0, does it? Wasn't that the > entire reason the original code went wrong? I don’t remember really, but presuming the conclusions of the discussion, seems it is fixed now. It was something about registers when using inline assembly. Anyway this works just fine on all my Haswell machines. Regards, -- Adam

hello, i rsynced a kvm vm from one host to another. i start virt-manager and tell virt-manager to use an existing disk. i set cpu to haswell that is on the host. configure before start is set, and i start "begin installation". I get this output by virt-manager: Unable to complete install: 'internal error: process exited while connecting to monitor: 2017-07-19T09:27:10.861928Z qemu-system-x86_64: can't apply global...

Hi Adam, > OK. I know the reason you cannot reproduce it, before posting > the patch I've decided to check for AVX before checking AVX2, > just not to cpuid AVX2 when we don't have AVX1 anyway. I suspect it was also incompetence on my part. Given the differences I'm seeing now I can't believe there'd be *no* difference in my tests if I'd done them properly.

> That's far more worrying to me than not being able to detect Haswell. > I can't reproduce the problem here at the moment: both debug and > release builds give identical assembly for Host.cpp. OK. I know the reason you cannot reproduce it, before posting the patch I've decided to check for AVX before checking AVX2, just not to cpuid AVX2 when we don...

Hi Adam, > * I have marked HasAVX2 as "volatile", since otherwise it gets > magically zeroed (by optimizer?) when compiling clang with latest > clang build from trunk That's far more worrying to me than not being able to detect Haswell. I can't reproduce the problem here at the moment: both debug and release builds give identical assembly for Host.cpp. I don't suppose you could post the command-line clang is using to build Host.cpp (and perhaps the differing object files if you have them handy)? Cheers. Tim.

> I don’t remember really, but presuming the conclusions of the discussion, seems it is fixed now. It was something about registers when using inline assembly. Anyway this works just fine on all my Haswell machines. I think that's more coincidence than anything else (something perturbed in your host compiler's backend). If you look at lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp there's a GetCpuIDAndInfoEx function which specifically sets %ecx to a valid value before executing "...

Hi I wonder, if live migration (back and forth) is possible on mixed Haswell (Xeon V3) and Broadwell (Xeon V4) installations. The only notable difference between the two is apparently a working TSX implementation on V4, which got disabled on V3 due to bugs. The rest (VMCS-shadowing, posted interrupts) should not apply to our environment, as we do not run nested-vmx nor...

...I wanted to post this to Xen WIKI, but I have no write rights there. I have talked to AsRock support, and they said, that: - all Z87, H87, Q87 and B85 asrock mainboards support vt-d, - you have to check if vt-d is supported by the CPU, - there are no information on vt-d support in future haswell mainboard chipsets, like H81. I''m willing to test it, when I get hands on a haswell mobo. Is this information of any value to you all? -- Pozdrawiam Jakub Kulesza _______________________________________________ Xen-users mailing list Xen-users@lists.xen.org http://lists.xen.org/xe...

I have a group of students working with me on some LLVM projects related to our Parabix research. One interesting issue that has come up for us is code generation support for the Haswell new instructions pext and pdep. These instructions shuffle bits within a 64-bit word, either gathering all selected bits to the beginning (pext) or scattering some initial bits throughout (pdep). A natural model for this is to use shufflevector on v32i1 and v64i1 vectors. We've got some p...

Here we go, updated patch following your advice checking max leaf and porting cpuidex for subleaf (ECX) 0. NOTE: I’ve set Haswell to be not only 60, but also 63, 69 & 70 model, following changes in Linux kernel & Xen. Also set 62 as Ivy Bridge EP aka E5 v3 (which I has in my workstation). Cheers, -- Adam Detects x86 family 6 model 60, 63, 69, 70 CPU that has AVX2 CPUID leaf 7 subleaf 0 AVX2 flag as core-avx2. Po...

...i, Nov 22, 2013 at 7:34 AM, Tim Northover <t.p.northover at gmail.com>wrote: > > I don’t remember really, but presuming the conclusions of the > discussion, seems it is fixed now. It was something about registers when > using inline assembly. Anyway this works just fine on all my Haswell > machines. > > I think that's more coincidence than anything else (something > perturbed in your host compiler's backend). If you look at > lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp there's a > GetCpuIDAndInfoEx function which specifically sets %ecx to a valid...

Hi all, Intel has just revealed its AVX2 instruction set, to be supported by the 2013 Haswell architecture, and it's looking quite revolutionary: http://software.intel.com/en-us/forums/showthread.php?t=83399 <http://software.intel.com/en-us/forums/showthread.php?t=83399&o=a&s=lr> &o=a&s=lr It includes powerful 'gather' instructions, which allow reading...

When doing repeated regressions on large data sets, I'm finding that the time spent on garbage collection often exceeds the time spent on the regression itself. Consider this test program which I'm running on an Intel Haswell i7-4470 processor under Linux 3.13 using R 3.1.2 compiled with ICPC 14.1: nate at haswell:~$ cat > gc.R library(speedglm) createData <- function(n) { int <- -5 x <- rnorm(n, 50, 7) e <- rnorm(n, 0, 1) y <- int + (1.2 * x) + e return(data.frame(y...

Hi , Created new thread . Environment: Bare Metal server + CentOs with qemu/KVM +libvirt for virtualization Guest Instantiated with virt-install with forced CPU model like below virt-install --virt-type kvm --name compute-0 --cpu Haswell,+fma,+movbe,+fsgsbase,+bmi1,+hle,+avx2,+smep,+bmi2,+erms,+invpcid,+rtm --ram=61440 --vcpus=20 --os-type=linux --os-variant=generic After guest installation /proc/cpuinfo show model name as Haswell . However Libvirt virsh capabilities show CPU configuration as "SandyBridge . " 1. Could...

...e load LLVM instruction to take "load pointer, offset", or by using a new "gather pointer, offset" LLVM instruction is a lesser issue IMO. Jose ----- Original Message ----- > Hi all, > Intel has just revealed its AVX2 instruction set, to be supported by > the 2013 Haswell architecture, and it's looking quite revolutionary: > http://software.intel.com/en-us/forums/showthread.php?t=83399&o=a&s=lr > It includes powerful 'gather' instructions, which allow reading > multiple vector elements from non-contiguous memory locations. It > also...

Hi Adam, > + bool HasAVX2 = HasAVX && !GetX86CpuIDAndInfo(0x7, &EAX, &EBX, &ECX, &EDX) && > + (EBX & 0x20); I don't think this guarantees %ecx is 0, does it? Wasn't that the entire reason the original code went wrong? Cheers. Tim.