llvm dev - Dec 2012 - [LLVMdev] Increase the number of registers in ARM

Hi,

I want to increase the number of integer registers in the ARM machine.
I don't have any idea how/where I can start. Can anybody help me?
By the way, what are the following line in the ARMRegisterInfo.td specify:

def qsub_0
def qsub_1
....

Thanks

Best Regards,
A. Yazdanbakhsh
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
PhD. Student
School of Electrical and Computer Engineering
University of Wisconsin-Madison
E-mail:     yazdanbakhsh at wisc.edu


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On Wed, Dec 05, 2012 at 09:17:12PM -0600, Amir Yazdanbakhsh
wrote:
> Hi,
> 
> I want to increase the number of integer registers in the ARM machine.
> I don't have any idea how/where I can start. Can anybody help me?
  The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
should look into,

// Integer registers
def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
  
  ...

HTH,
chenwj

-- 
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote:
>  The code below in lib/Target/ARM/ARMRegisterInfo.td is where you
> should look into,
> 
> // Integer registers
> def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
> def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
> 
>  ...
That's the easy part.  ARM (AArch32) has 16 registers because register
operands are stored in a 4-bit bitfield in the instructions.  If you want to add
more registers, then you will also need to modify the instruction encoding of
every instruction, or place them in a separate namespace (as with the NEON / VFP
registers) and add instructions for explicitly modifying them.

David