llvm dev - Jul 2011 - [LLVMdev] code generation removes duplicated instructions

Hello,

I am duplicating few instructions in a basic block and splitting it. The
following is an example.

bb:                                               ; preds = %bb1
  %0 = load i32* %i, align 4
  %1 = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
  store i32 0, i32* %1, align 4
  %2 = load i32* %i, align 4
  %3 = getelementptr inbounds [100 x i32]* %last_added, i32 0, i32 %2
  store i32 -1, i32* %3, align 4
  %4 = load i32* %i, align 4
  %5 = add nsw i32 %4, 1
  store i32 %5, i32* %i, align 4
  br label %bb1

==>

  %0 = load i32* %i, align 4
  %HV14_ = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
  %1 = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
  %HVCmp7 = icmp ne i32* %1, %HV14_
  br i1 %HVCmp7, label %relExit, label %bb.split

So that HV14_ is a new instruction and I am inserting a comparison to jump
to a newly created basic block. Somehow the code generation for arm removes
the duplicated instruction and cmp instruction in arm assembly looks as
follows.

cmp r0, r0

This defeats the purpose of doing the duplication in the first place. Does
anyone have any insight on this? Can anyone suggest some starting points to
debug this?


Thanks a lot.
Daya
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On 6 July 2011 02:31, D S Khudia <daya.khudia at gmail.com>
wrote:
>   %0 = load i32* %i, align 4
>   %HV14_ = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
>   %1 = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
>   %HVCmp7 = icmp ne i32* %1, %HV14_
>   br i1 %HVCmp7, label %relExit, label %bb.split
>
> So that HV14_ is a new instruction and I am inserting a comparison to jump
> to a newly created basic block. Somehow the code generation for arm removes
> the duplicated instruction and cmp instruction in arm assembly looks as
> follows.
> cmp r0, r0
Hi Daya,

This is perfectly legal, since the two registers have exactly the same
value (a[i]) and the comparison will always be the same.

I suppose the rest of the original IR (the other array load, the
stores and the increment) are in the branched basic blocks...

> This defeats the purpose of doing the duplication in the first place. Does
> anyone have any insight on this? Can anyone suggest some starting points to
> debug this?
What is the purpose of the duplication?

cheers,
--renato

Thank you for replying. Yes. The remaining part of the BB is in splitted
basic block.

The following is an example code generation for arm and x86 for a same IR
BB. In the x86 code I can see that the same computation is done twice and
result is stored in two different registers and then these two different
registers are used for comparision. By the way I am duplicating instruction
and inserting comparison to catch transient errors.

IR BB:

bb:                                               ; preds = %bb1.split
  %0 = load i32* %i, align 4
  %HV10_ = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
  %1 = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
  %HVCmp15 = icmp ne i32* %1, %HV10_
  br i1 %HVCmp15, label %relExit, label %bb.split

x86 asm:

.LBB0_1:                                # %bb
                                        #   in Loop: Header=BB0_5 Depth=1
  leal  972(%esp), %eax
  movl  568(%esp), %ecx
  imull $4, %ecx, %edx
  addl  %eax, %edx
  imull $4, %ecx, %ecx
  addl  %eax, %ecx
  cmpl  %edx, %ecx
  movl  %ecx, 508(%esp)         # 4-byte Spill
  jne .LBB0_88

arm asm:

.LBB0_1:                                @ %bb
                                        @   in Loop: Header=BB0_5 Depth=1
  ldr r0, [sp, #444]
  add r1, sp, #53, 28         @ 848
  add r0, r1, r0, lsl #2
  cmp r0, r0
  str r0, [sp, #384]
  bne .LBB0_88
  b .LBB0_2

Thanks
Daya

On Wed, Jul 6, 2011 at 6:18 AM, Renato Golin <renato.golin at arm.com>
wrote:
> On 6 July 2011 02:31, D S Khudia <daya.khudia at gmail.com> wrote:
> >   %0 = load i32* %i, align 4
> >   %HV14_ = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
> >   %1 = getelementptr inbounds [100 x i32]* %a, i32 0, i32 %0
> >   %HVCmp7 = icmp ne i32* %1, %HV14_
> >   br i1 %HVCmp7, label %relExit, label %bb.split
> >
> > So that HV14_ is a new instruction and I am inserting a comparison to
> jump
> > to a newly created basic block. Somehow the code generation for arm
> removes
> > the duplicated instruction and cmp instruction in arm assembly looks
as
> > follows.
> > cmp r0, r0
>
> Hi Daya,
>
> This is perfectly legal, since the two registers have exactly the same
> value (a[i]) and the comparison will always be the same.
>
> I suppose the rest of the original IR (the other array load, the
> stores and the increment) are in the branched basic blocks...
>
>
> > This defeats the purpose of doing the duplication in the first place.
> Does
> > anyone have any insight on this? Can anyone suggest some starting
points
> to
> > debug this?
>
> What is the purpose of the duplication?
>
> cheers,
> --renato
>
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