llvm dev - Jul 2008 - [LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC

Hi Evan,

Evan Cheng wrote:
> The patch looks great. But I do have one comment:
> 
> +let usesCustomDAGSchedInserter = 1 in {
> +  let Uses = [CR0] in {
> +    let Uses = [R0] in
> +    def ATOMIC_LOAD_ADD_I32 : Pseudo<
> 
> The "let Uses = [R0]" is not needed. The pseudo instruction will
be
> expanded like this later:
> 
> +    BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
> +      .addReg(ptrA).addReg(ptrB);
> +    BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
> +      .addReg(incr).addReg(dest);
> +    BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
> +      .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);
> 
> The second instruction defines R0 and the 3rd reads R0 which is
> enough to tell the register allocator what to do.
> 
> I do have a question, must it use R0? If it's not fixed, it's
> probably better to create a new virtual register and use that
> instead.
It's not fixed.  How do I create a new virtual register?  This is my
first real go at adding to LLVM, so I'm kind of figuring it out as I
go along :)

Cheers,
Gary

-- 
http://gbenson.net/

Look for createVirtualRegister. These are examples in  
PPCISelLowering.cpp.

Evan
On Jul 8, 2008, at 8:24 AM, Gary Benson wrote:
> Hi Evan,
>
> Evan Cheng wrote:
>> The patch looks great. But I do have one comment:
>>
>> +let usesCustomDAGSchedInserter = 1 in {
>> +  let Uses = [CR0] in {
>> +    let Uses = [R0] in
>> +    def ATOMIC_LOAD_ADD_I32 : Pseudo<
>>
>> The "let Uses = [R0]" is not needed. The pseudo instruction
will be
>> expanded like this later:
>>
>> +    BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
>> +      .addReg(ptrA).addReg(ptrB);
>> +    BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
>> +      .addReg(incr).addReg(dest);
>> +    BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
>> +      .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);
>>
>> The second instruction defines R0 and the 3rd reads R0 which is
>> enough to tell the register allocator what to do.
>>
>> I do have a question, must it use R0? If it's not fixed, it's
>> probably better to create a new virtual register and use that
>> instead.
>
> It's not fixed.  How do I create a new virtual register?  This is my
> first real go at adding to LLVM, so I'm kind of figuring it out as I
> go along :)
>
> Cheers,
> Gary
>
> -- 
> http://gbenson.net/
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

Cool, thanks, I'll check that out.

Cheers,
Gary

Evan Cheng wrote:
> Look for createVirtualRegister. These are examples in  
> PPCISelLowering.cpp.
> 
> Evan
> On Jul 8, 2008, at 8:24 AM, Gary Benson wrote:
> 
> > Hi Evan,
> >
> > Evan Cheng wrote:
> >> The patch looks great. But I do have one comment:
> >>
> >> +let usesCustomDAGSchedInserter = 1 in {
> >> +  let Uses = [CR0] in {
> >> +    let Uses = [R0] in
> >> +    def ATOMIC_LOAD_ADD_I32 : Pseudo<
> >>
> >> The "let Uses = [R0]" is not needed. The pseudo
instruction will be
> >> expanded like this later:
> >>
> >> +    BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX),
dest)
> >> +      .addReg(ptrA).addReg(ptrB);
> >> +    BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8),
PPC::R0)
> >> +      .addReg(incr).addReg(dest);
> >> +    BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
> >> +      .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);
> >>
> >> The second instruction defines R0 and the 3rd reads R0 which is
> >> enough to tell the register allocator what to do.
> >>
> >> I do have a question, must it use R0? If it's not fixed,
it's
> >> probably better to create a new virtual register and use that
> >> instead.
> >
> > It's not fixed.  How do I create a new virtual register?  This is
my
> > first real go at adding to LLVM, so I'm kind of figuring it out as
I
> > go along :)
> >
> > Cheers,
> > Gary
> >
> > -- 
> > http://gbenson.net/
> > _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
-- 
http://gbenson.net/

Would it be acceptable to change MachineInstr::getRegInfo from private
to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter?

Cheers,
Gary

Evan Cheng wrote:
> Look for createVirtualRegister. These are examples in  
> PPCISelLowering.cpp.
> 
> Evan
> On Jul 8, 2008, at 8:24 AM, Gary Benson wrote:
> 
> > Hi Evan,
> >
> > Evan Cheng wrote:
> >> The patch looks great. But I do have one comment:
> >>
> >> +let usesCustomDAGSchedInserter = 1 in {
> >> +  let Uses = [CR0] in {
> >> +    let Uses = [R0] in
> >> +    def ATOMIC_LOAD_ADD_I32 : Pseudo<
> >>
> >> The "let Uses = [R0]" is not needed. The pseudo
instruction will be
> >> expanded like this later:
> >>
> >> +    BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX),
dest)
> >> +      .addReg(ptrA).addReg(ptrB);
> >> +    BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8),
PPC::R0)
> >> +      .addReg(incr).addReg(dest);
> >> +    BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
> >> +      .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);
> >>
> >> The second instruction defines R0 and the 3rd reads R0 which is
> >> enough to tell the register allocator what to do.
> >>
> >> I do have a question, must it use R0? If it's not fixed,
it's
> >> probably better to create a new virtual register and use that
> >> instead.
> >
> > It's not fixed.  How do I create a new virtual register?  This is
my
> > first real go at adding to LLVM, so I'm kind of figuring it out as
I
> > go along :)
> >
> > Cheers,
> > Gary
> >
> > -- 
> > http://gbenson.net/
> > _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
-- 
http://gbenson.net/