search for: gprc

...pile by changing to: > def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, > SDTCisSameAs<0, 1>]>; > def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; > > let Uses= [GRP] in { > def RelAddr : XSTGPseudo< (outs GPRC:$dst), > (ins GPRC:$spoff, GPRC:$addr), > "! RELADDR $spoff, $dst", > [(set GPRC:$dst, (XSTGRELADDR > GPRC:$addr, GPRC:$spoff))]>; > } > > ...though...

...==// def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; let Uses= [GRP] in { def RelAddr : XSTGPseudo< (outs), (ins GPRC:$spoff, GPRC:$dst), "! RELADDR $spoff, $dst", [(XSTGRELADDR GPRC:$spoff, GPRC: $dst)]>; } (specifically that 'def RelAddr' line) If I change it to have an empty pattern match like this: let Uses= [GR...

Hi all, I'm trying to figure out how to add the instructions required for llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:$label),...

But don't the defs for ADDR_RR and ADDR_RI also contain dags? def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; Do I need to create some other intermediate node type for a shifted address? Phil On Mon, Sep 26, 2016 at 1:42 PM, Krzysztof Parzyszek via llvm-...

...ncName, dag opInfo > : Operand<i64>, ComplexPattern< i64, numArgs, funcName, [], [SDNPWantParent] > { let MIOperandInfo = opInfo; } let PrintMethod = "printMemOperand" in { def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; def ADDR_SHLI : Addr< 2, "SelectAddrShlImm", (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >; } If I...

Hi all, I have problem with specifying complex patterns in PPC Isel backend. I would like to fetch few instructions into one like that: def MatchPAT1 : Pat<(or (or (shl GPRC:$rA, (i32 imm:$imm24)), (and (shl GPRC:$rA, (i32 imm:$imm8)), 0xFF0000) ), (or (srl GPRC:$rA, (i32 imm:$imm24)), (and (shl GPRC:$rA, (i32 imm:$imm8)),0xFF00) )), (myinstr GPRC:$rA)>; That pattern corresponds to i32 bswap intrinsic. The thing is that such complex pattern matching...

...ruction fields are populated. Perhaps I'm just being dense, but I cannot see how SDAG operands are translated into the encoding fields. Can someone please explain the following snippet from the PPC back-end. The AND instruction in PPC is defined as: 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1012 "and $rA, $rS, $rB", IntSimple, 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; Okay, so rA, rS, and rB are register operands. The TableGen classes are defined as: 315 class XForm_base_r3xo_swapped 316...

On Thu, Jan 7, 2016 at 1:35 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org > wrote: > On 1/7/2016 3:25 PM, Phil Tomson wrote: > >> >> That's better, but now I get: >> >> XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires >> exactly 2 operands! >> >> Which makes some sense as XSTGRELADDR is defined as: >> def

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and I can't figure out the s...

...mpletely understand), and the register allocator tries to spill the count register. For example, with strong-phi elimination, I get (as a simple example): BB#0: derived from LLVM BB %entry Live Ins: %X3 %vreg2<def> = COPY %X3<kill>; G8RC:%vreg2 %vreg4<def> = LI 2048; GPRC:%vreg4 %vreg3<def> = OR8To4 %vreg2<kill>, %vreg2; GPRC:%vreg3 G8RC:%vreg2 %vreg9<def> = COPY %vreg4<kill>; GPRC:%vreg9,%vreg4 %vreg10<def> = RLDICL %vreg9<kill>, 0, 32; GPRC:%vreg10,%vreg9 %vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vre...

...zysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 9/26/2016 3:58 PM, Phil Tomson wrote: > >> But don't the defs for ADDR_RR and ADDR_RI also contain dags? >> >> def ADDR_RR : Addr< 2, "SelectAddrRegReg", >> (ops GPRC:$base, GPRC:$offsetreg) >; >> def ADDR_RI : Addr< 2, "SelectAddrRegImm", >> (ops GPRC:$base, i64imm:$offsetimm) >; >> >> Do I need to create some other intermediate node type for a shifted >> address? >> > > Techni...

Hi, In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register: class isDOT { list<Register> Defs = [CR0]; bit RC = 1; } and this gets used on instructions such as: def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic. $rD, $rA, $imm", IntGeneral, []>, isDOT; but there is a small problem. If these instructions are also part of a larger block which also defines registers, like this: let Defs = [CARRY] in def ADDICo...

..., but I cannot see how SDAG operands are translated into > > the encoding fields. Can someone please explain the following snippet > from > > the PPC back-end. > > > > The AND instruction in PPC is defined as: > > > > 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, > GPRC:$rB), > > 1012 "and $rA, $rS, $rB", IntSimple, > > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; > > > > Okay, so rA, rS, and rB are register operands. > > > > The TableGen clas...

...Cheers, Gary Evan Cheng wrote: > Just cast both values to const TargetRegisterClass*. > > Evan > > On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > > Evan Cheng wrote: > > > How about? > > > > > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > > > &PPC:G8RCRegClass; > > > unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > > > I tried something like that yesterday: > > > > const TargetRegisterClass *RC = > > is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass;...

...o instructions that can span multiple basic blocks. See PPCTargetLowering::EmitInstrWithCustomInserter(). Evan On Jun 30, 2008, at 6:10 AM, Gary Benson wrote: > Chris Lattner wrote: >> On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: >>> def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: >>> $label), >>> "cmpw $rA, $rB\n\tbne- La${label}_exit", >>> [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: >>> $label)]>; >>> } >>> >>> ...and I can't...

...aps I'm > just being dense, but I cannot see how SDAG operands are translated into > the encoding fields. Can someone please explain the following snippet from > the PPC back-end. > > The AND instruction in PPC is defined as: > > 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), > 1012 "and $rA, $rS, $rB", IntSimple, > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; > > Okay, so rA, rS, and rB are register operands. > > The TableGen classes are defined as: > > 31...

...operands are translated into >> > the encoding fields. Can someone please explain the following snippet >> from >> > the PPC back-end. >> > >> > The AND instruction in PPC is defined as: >> > >> > 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, >> GPRC:$rB), >> > 1012 "and $rA, $rS, $rB", IntSimple, >> > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; >> > >> > Okay, so rA, rS, and rB are register operands. >> > &gt...

...ot;XSTGISD::MVINI", SDT_XSTGMVINI>; def SDT_RELADDR : SDTypeProfile<1, 2, []>; def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; let Constraints = "$dst = $addr", Uses= [GRP] in { def RelAddr : XSTGPseudo< (outs GPRC:$dst), //(ins GPRC:$spoff, GPRC:$addr), (ins i64imm:$spoff, i64imm:$addr), "! RELADDR $spoff, $dst", [(set GPRC:$dst, (XSTGRELADDR i64:$s...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...ould expand to a conditional move (moveq for example). Something similar is done by the Alpha backend: --------------------------------------------------------------------------------------------- def CMOVEQ : OForm4< 0x11, 0x24, "cmoveq $RCOND,$RTRUE,$RDEST", [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>; ---------------------------------------------------------------------------------------------- One thing that I don't understand is how the $RFALSE value is used. $RDEST must equal $RFALSE before the cmov is exec...