llvm dev - Oct 2006 - [LLVMdev] Implicit defs

Hi,

Is it possible to dynamically define implicit defs for some
instructions?
Concretely, I'd like to define a register for a return value of a call
in a dynamic way, instead of using current static approach looking
like:
 let Defs = [R0] in 
 def CALLimm :  I<...>;

The reason for this wish is that some of the calling conventions on my
target use different sets of physical registers for their return
values. Therefore I cannot describe it by one static set of regs, as
shown above.

By looking into LLVM code, I've found how to force some arguments of
calls to be placed on required registers and how to copy the result of
the call from certain (return) registers. But if I try to copy from a
return register that is not in the static Defs set of the CALL machine
instruction, then register allocator complains that the interval for a
return value of a CALL does not exist. Which means that the register
allocator does not understand that this register is implicitly defined
by the CALL insn.

One obvious solution is to define several machine instructions for a
CALL, each defining its own set of implicitly defined registers. But it
is not very elegent in my opinion. Are there any other ways to achieve
the same result? May be it can be solved simpler?

Thanks,
 -Roman



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Hi Chris,

Thanks for your response.
> On Sat, 14 Oct 2006, Roman Levenstein wrote:
> > Is it possible to dynamically define implicit defs for some
> > instructions?
> 
> Yes!  This is what explicit operands are :).  Specifically, if you
> want to 
> vary on a per-opcode basis what registers are used/def'd by the 
> instruction, you can just add those registers as explicit use/def
> operands 
> in the machine instruction with the physical registers directly
> filled in.
OK. I have not explained in my first email about DEFs everything I
wanted, the second one was a bit more specific ;) Of course, I realize
that I can add explicit DEFs to the machine instruction. But is it
possible to do it at the higher level, e.g. in the ISelLowering passes,
where no machine insns are generated yet. Basically, it is currently
possible at this level to do the mapping of virtual registers for
parameters to the physical registers, and this can be done without any
problems. It is usually done in  LowerCALL or something like that. I'd
like to do the same for return registers at the same place, to keep all
these related things together and because of certain symmetry of goals.
But if I would do it as you propose, I'll need to put somewhere else,
where we can operate at  the MI level, right? So the question is
actually about possibility of doing it in LowerCALL, where MIs are not
generated yet. 
  
P.S. Chris, have you seen this mail from me on the mailing list?
http://lists.cs.uiuc.edu/pipermail/llvmdev/2006-October/006937.html
There was no reply, so I'm not sure if it is because there are no
comments or may be because it was overseen.

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