search for: callopc

Displaying 3 results from an estimated 3 matches for "callopc".

Did you mean: calloc
2006 Oct 16
0
[LLVMdev] Implicit defs
...hey are known live // into the call. for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); if (InFlag.Val) Ops.push_back(InFlag); Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); This creates a call node with a list of input registers, these are marked as uses. In the PPC backend, this is matched with this pattern: ... def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), "bla $func",...
2006 Oct 15
2
[LLVMdev] Implicit defs
Hi Chris, Thanks for your response. > On Sat, 14 Oct 2006, Roman Levenstein wrote: > > Is it possible to dynamically define implicit defs for some > > instructions? > > Yes! This is what explicit operands are :). Specifically, if you > want to > vary on a per-opcode basis what registers are used/def'd by the > instruction, you can just add those registers
2015 Jan 11
3
[LLVMdev] [RFC] [PATCH] add tail call optimization to thumb1-only targets
...+1810,12 @@ } } + if (CallAdressShallBeForcedToHardRegR12) { + Chain = DAG.getCopyToReg(Chain, dl, ARM::R12, + Callee,Chain.getValue(1)); + Callee = DAG.getRegister (ARM::R12,getPointerTy()); + } + // FIXME: handle tail calls differently. unsigned CallOpc; bool HasMinSizeAttr = MF.getFunction()->getAttributes().hasAttribute( @@ -2000,26 +2031,6 @@ if (isCalleeStructRet || isCallerStructRet) return false; - // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: - // emitEpilogue is not ready for them. Thumb tail...