search for: gettargetconst

...its not pretty. First make i64 not be legal. Then, assuming the regclass you gave has some subregs, you can give load/store a custom legalisation where you change the i64 to MVT::Untyped. So something like this for ISD::STORE: SDValue ValueToBeStored = St.getOperand(…) auto SeqOps[] = { DAG.getTargetConstant(SP::IntPairRegClassID, MVT::i32), DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(0, MVT::i32)), DAG.getTargetConstant(SP ::sub0, MVT::i32), DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(1, MVT::i32)), DAG.getTargetConst...

.... Then, assuming the regclass you gave has some subregs, you can give load/store a custom legalisation where you change the i64 to MVT::Untyped. So something like this for ISD::STORE: >> >> SDValue ValueToBeStored = St.getOperand(…) >> >> auto SeqOps[] = { >> DAG.getTargetConstant(SP::IntPairRegClassID, MVT::i32), >> DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(0, MVT::i32)), >> DAG.getTargetConstant(SP ::sub0, MVT::i32), >> DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(1, MVT::i32...

...or result and Intrinsic ID), can't seem to find what cast is causing the issue here. On Fri, Jun 24, 2016 at 11:47 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > That's what I thought but I got the same error with: > > DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, > DAG.getTargetConstant(Intrinsic::my_intrinsic, DL, MVT::i16), LHS); > > Thanks. > > What should this call look like? > > > On Fri, Jun 24, 2016 at 10:53 AM, <escha at apple.com> wrote: > >> The intrinsic ID is an int, not a float. >> >> —escha >> >> On Jun 2...

....4 is no longer building on OS X Leopard (https://trac.macports.org/ticket/41548). It seems the issue is with a commit that you made back in April (referenced below) which added this to SIISelLowering.cpp: // Adjust the writemask in the node std::vector<SDValue> Ops; Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) Ops.push_back(Node->getOperand(i)); Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size()); That fails with Leopard's libstdc++ STL which does not a data method for std::ve...

In SelectionDAG, what's the difference between getConstant and getTargetConstant? One creates a node with opcode Constant and the other with TargetConstant. What's the semantic difference? In X86ISelLowering I need to create a constant vector and put it in memory so I can reference it as an operand. I don't see any examples of doing this. Is it possible? If so,...

...I am writing a back end for CortexM0 (for self teaching purposes), I am working on LDR with immediate offset instruction. In the ARM backend, if the offset is 0, the following code is executed by the function ARMDAGToDAGISel::SelectThumbAddrModeImm5S Base = N.getOperand(0); OffImm = CurDAG->getTargetConstant(0, MVT::i32); If I do a similar thing in my backend, I get this assertion message. I found out that if I execute the code below, the problem disappear. Base = N; OffImm = CurDAG->getTargetConstant(0, TM.getTargetLowering()->getPointerTy()); Only the change for Base seems relevant to...

On Sat, 14 Oct 2006, Roman Levenstein wrote: >> On Sat, 14 Oct 2006, Roman Levenstein wrote: >>> Is it possible to dynamically define implicit defs for some >>> instructions? >> >> Yes! This is what explicit operands are :). Specifically, if you >> want to >> vary on a per-opcode basis what registers are used/def'd by the >> instruction,

...k; ... SDValue Ops[6]; SDValue chain = Op.getOperand(0); unsigned numNodes = 0; if (inChain) { Ops[numNodes++] = chain; } SDValue Chain = Op.getOperand(0); Ops[numNodes++] = Op.getOperand((inChain) ? 2 : 1); Ops[numNodes++] = DAG.getConstant(1, MVT::i32); Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32); Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes); if (outChain) { SDValue mv[2] = {Op, chain}; Op = DAG.getMergeValues(mv, 2, dl); } return Op; } I'm guessing I am not handling the chain correctly, but I'm not sure what I am doing wrong. Can s...

...pattern. The following code snippet is not really working for me: SDValue rvexTargetLowering:: LowerAddCG(SDValue Op, SelectionDAG &DAG) const { unsigned Opc = Op.getOpcode(); SDNode* N = Op.getNode(); EVT VT = Op.getValueType(); DebugLoc dl = N->getDebugLoc(); SDValue BReg = DAG.getTargetConstant(rvex::B0, VT); // Add extra register to output return DAG.getNode(rvexISD::Addc, dl, VT, N->getOperand(0), N->getOperand(1), BReg); } Could anybody advice me on a way to make the backend know that the ADDE instruction will cause a branch register to be used? Thanks in advance! Maur...

Hi Chris, Thanks for your response. > On Sat, 14 Oct 2006, Roman Levenstein wrote: > > Is it possible to dynamically define implicit defs for some > > instructions? > > Yes! This is what explicit operands are :). Specifically, if you > want to > vary on a per-opcode basis what registers are used/def'd by the > instruction, you can just add those registers

Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya

...lding on OS X Leopard (https://trac.macports.org/ticket/41548). It seems the issue is with a commit that you made back in April (referenced below) which added this to SIISelLowering.cpp: > > // Adjust the writemask in the node > std::vector<SDValue> Ops; > Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); > for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) > Ops.push_back(Node->getOperand(i)); > Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size()); > > That fails with Leopard's libstdc++ STL which does not a...

The code below is triggering some weird behavior that's different from how gcc treats this inline asm. Clang keeps the original type of "loc" as "bool", which generates an "i1 true" after inlining. So far so good. However, during ISEL, the "true" is converted to a signed integer. So when it's evaluated, the result is this: .quad

In http://reviews.llvm.org/D8713, I added the 64bit integer store ("std") and load ("ldd") instructions for 32bit sparc. But now I need codegen to know how to emit them, and am not sure the best way to go about teaching the backend that 64bit integers can be used natively, but only for loads and stores. (I originally wrote an earlier draft of question in the review but it

...= Op.getOperand(0); > unsigned numNodes = 0; > if (inChain) { > Ops[numNodes++] = chain; > } > SDValue Chain = Op.getOperand(0); > Ops[numNodes++] = Op.getOperand((inChain) ? 2 : 1); > Ops[numNodes++] = DAG.getConstant(1, MVT::i32); > Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32); > Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes); > if (outChain) { > SDValue mv[2] = {Op, chain}; > Op = DAG.getMergeValues(mv, 2, dl); > } > return Op; > } > > I’m guessing I am not handling the chain correctly, but I’m...

...d numNodes = 0; > > if (inChain) { > > Ops[numNodes++] = chain; > > } > > SDValue Chain = Op.getOperand(0); > > Ops[numNodes++] = Op.getOperand((inChain) ? 2 : 1); > > Ops[numNodes++] = DAG.getConstant(1, MVT::i32); > > Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32); > > Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes); > > if (outChain) { > > SDValue mv[2] = {Op, chain}; > > Op = DAG.getMergeValues(mv, 2, dl); > > } > > return Op; > > } > > > > I'm guessing...

...tting a casting issue, my code is: > > SDValue XXXLowering::LowerFSQRT(SDValue Op, SelectionDAG &DAG) const { > SDLoc DL(Op); > EVT VT = Op.getValueType(); > SDValue LHS = Op.getOperand(0); > > SDValue newNode = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, DAG.getTargetConstantFP(Intrinsic::my_intrinsic, DL, VT), LHS); > return newNode; > } > > The error I'm getting is: Assertion 'isa<X>(Val) && "cast<Ty>() argument of incompatible type!" > > Is this the correct way to add intrinsic dag node? > > Thank...

...); Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), inc, InFlag); InFlag = Chain.getValue(1); Unfortunately, this becomes movl $42, %eax 1) That is, the ADD-operation is being folded. Is there a way to prevent this from happening? I tried creating the constants wit DAG::getTargetConstant, but it didn't help. 2) The second thing in this code is that InFlag. If I don't place InFlag = SDValue(); there, llc complains about wrong topological ordering. What's that about? Related to that: If I recover the Flag-result from the Chain by InFlag = Chain.getValue(1);, what is i...

On Jul 1, 2009, at 2:22 PMPDT, Dan Gohman wrote: >> Ops.push_back(DAG.getConstant(1, MVT::i32)); >> Chain = DAG.getNode(ISD::ADD, DAG.getVTList(MVT::Other, MVT::i32), >> &Ops[0], Ops.size()); >> >> Isn't that the way how it is supposed to work? > > ADD does not use a chain, so there's no chain operand, or > MVT::Other result for it in an ADD

...Node<null> (MetaData) with a ch out port SDNode *mdNodeSDNode = CurDAG->getNode(ISD::MDNODE_SDNODE, DL, CurDAG->getVTList(MVT::Other)).getNode(); opsRes.push_back(SDValue(mdNodeSDNode, 0)); SDValue targetConstant = CurDAG->getTargetConstant(1, DL, MVT::i64); SDNode *targetConstantSDNode = targetConstant.getNode(); opsRes.push_back(SDValue(targetConstantSDNode, 0)); SDValue inlineAsm = CurDAG->getNode(ISD::INLINEASM, DL, CurDAG->getVTList(MVT::Other, MVT::Glue),...