search for: regstopass

...ISD::ExtractElementF64, dl, MVT::i32, Arg, DAG.getConstant(1, MVT::i32)); if (!Subtarget->isLittle()) std::swap(Lo, Hi); unsigned LocRegLo = VA.getLocReg(); unsigned LocRegHigh = getNextIntArgReg(LocRegLo); RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); I added this SDValue: SDValue Num = DAG.getNode(MIPSISD::CopyF64,dl,MVT::i32, Arg); But I need to create a Hi and a Lo SDValue to add to the RegsToPass pairs seen in the code above. If so...

...'t reference a > where or how? the register uses are added by the function X86TargetLowering::LowerCall() during the DAG Lowering phase. This is the relevant code segment: // Add argument registers to the end of the list so that they are known live // into the call. for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); Regards, Christoph

...yet. This is certainly possible, but requires some C++ code. I assume you have something like the PPC backend right now. If so, you have this in your lowering code: // Add argument registers to the end of the list so that they are known live // into the call. for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); if (InFlag.Val) Ops.push_back(InFlag); Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); This creates a call node with a l...

...Arg, DAG.getConstant(1, MVT::i32)); > > if (!Subtarget->isLittle()) > std::swap(Lo, Hi); > > unsigned LocRegLo = VA.getLocReg(); > unsigned LocRegHigh = getNextIntArgReg(LocRegLo); > > RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); > RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); > > I added this SDValue: > SDValue Num = DAG.getNode(MIPSISD::CopyF64,dl,MVT::i32, Arg); > > Doesn't this code violate SDT_MipsCopyF64's constraint? CopyF64'...

Hi Chris, Thanks for your response. > On Sat, 14 Oct 2006, Roman Levenstein wrote: > > Is it possible to dynamically define implicit defs for some > > instructions? > > Yes! This is what explicit operands are :). Specifically, if you > want to > vary on a per-opcode basis what registers are used/def'd by the > instruction, you can just add those registers

In X86InstrInfo.td for Call Instructions, it mentions that Uses for argument registers are added manually. Can someone point me to the location where they are added as the comment doesn't reference a where or how? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL:

Ping. Anyone that works on the x86 backend have an answer for this one? Thanks, Micah From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Thursday, June 10, 2010 1:40 PM To: LLVM Developers Mailing List Subject: [LLVMdev] Question on X86 backend In X86InstrInfo.td for Call Instructions, it mentions that Uses for argument registers are

...to [r2]). So if LLVM normally guesses these things automatically from the instructions, it wouldn't be able to guess that. But here I'm just conjecturing - may not be relevant! Thanks, Stephen [1]: LowerCall ... // Arguments that can be passed in a register must be kept in the // RegsToPass vector. if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); } else { // Sanity check. assert(VA.isMemLoc()); // Get the stack pointer if needed. if (StackPtr.getNode() == 0) { StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP...

...'t reference a > where or how? the register uses are added by the function X86TargetLowering::LowerCall() during the DAG Lowering phase. This is the relevant code segment: // Add argument registers to the end of the list so that they are known live // into the call. for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); Regards, Christoph _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu ht...

...of call lowering? if (isPPC64 && Arg.getValueType() == MVT::i32) { // FIXME: Should this use ANY_EXTEND if neither sext nor zext? @@ -1946,7 +2285,13 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, if (GPR_idx != NumGPRs) { RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + if (!isTailCall) + MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + // Calculate and remember argument location...

...if (isPPC64 && Arg.getValueType() == MVT::i32) { > // FIXME: Should this use ANY_EXTEND if neither sext nor zext? > @@ -1946,7 +2285,13 @@ SDOperand > PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, > if (GPR_idx != NumGPRs) { > RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); > } else { > - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, > 0)); > + if (!isTailCall) > + MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, > NULL, 0)); > + // Cal...

Hello Dale, this is an updated version of the tail call optimization patch for powerpc. could you have a look at it? i added code to support ppc64 (untested, will try to get access to ppc64 on a friend's machine). incorporated evan's formatting suggestions. ;) will run another round of testing (llvm-test) on my powerpc g4/800 when i get the okay to commit. testing on this machine takes

Hi, When using Wine to run Windows ARM64 executables on Linux, there's one major ABI incompatibility between the two; Windows treats the x18 register as the reserved platform register, while it is free to be clobbered anywhere in code on Linux. The Wine code sets up this register before passing control over to the Windows executable code, but whenever the Windows code calls a function

...amp;& Arg.getValueType() == MVT::i32) { >> // FIXME: Should this use ANY_EXTEND if neither sext nor zext? >> @@ -1946,7 +2285,13 @@ SDOperand >> PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, >> if (GPR_idx != NumGPRs) { >> RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); >> } else { >> - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, >> 0)); >> + if (!isTailCall) >> + MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, >> NULL, 0)); &gt...

...ering.cpp (Revision 225589) +++ ARMISelLowering.cpp (Arbeitskopie) @@ -1671,6 +1671,26 @@ InFlag = SDValue(); } + // For thumb1 targets, if R3 is used for argument passing, we need + // to place the call target address in IP (i.e. R12). + bool IsR3UsedForArgumentPassing = false; + if (RegsToPass.size() >= 4) { + IsR3UsedForArgumentPassing = true; + } + + bool IsCallAddressMoveToRegisterRequired = false; + bool CallAdressShallBeForcedToHardRegR12 = false; + + if (EnableARMLongCalls || (isTailCall && Subtarget->isThumb1Only() )) + { + IsCallAddressMoveToRegisterRequi...