llvm dev - Nov 2017 - question: access IR class Instruction from DAG SDValue

The llvm backend uses class Instruction in IR handle stage, create SDVaule and
DAG in DAG translation stage and class MachineInstr in Machine instruction
translation stage.
Can I access class Instruction from DAG structure or stage, or access DAG and
Instruction from MachineInstr structure or stage?

Jonathan

>From SDNode and MachineInstr class, I see no link between them and
IR/SDNode. The other places you can check are SelectionDAGBuilder [1] and
InstrEmitter [1], which responsible for translating IR to SDNode, and
SDNode to MachineInstr respectively.

I know you can retrieve the corresponding BasicBlock for a
MachineBasicBlock, which is easy. However, since we will do lowering and
combine during IR to SDNode transformation, I think it's hard to track the
relationship. Not sure it's the same for SDNode to MachineInstr
transformation, though.

[1] http://llvm.org/doxygen/classllvm_1_1SelectionDAGBuilder.html
[2] http://llvm.org/doxygen/classllvm_1_1InstrEmitter.html

2017-11-26 8:58 GMT+08:00 Jonathan via llvm-dev <llvm-dev at
lists.llvm.org>:
> The llvm backend uses class Instruction in IR handle stage, create SDVaule
> and DAG in DAG translation stage and class MachineInstr in Machine
> instruction translation stage.
> Can I access class Instruction from DAG structure or stage, or access DAG
> and Instruction from MachineInstr structure or stage?
>
> Jonathan
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>


-- 
Wei-Ren Chen (陳韋任)
Homepage: https://people.cs.nctu.edu.tw/~chenwj
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It might be a more useful to know what it is you need from the IR in the
DAG or what it is you r trying to do?



On Nov 25, 2017 7:59 PM, "Jonathan via llvm-dev" <llvm-dev at
lists.llvm.org>
wrote:
> The llvm backend uses class Instruction in IR handle stage, create SDVaule
> and DAG in DAG translation stage and class MachineInstr in Machine
> instruction translation stage.
> Can I access class Instruction from DAG structure or stage, or access DAG
> and Instruction from MachineInstr structure or stage?
>
> Jonathan
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
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I am working on llvm gpu backend. The instruction metadata can only get in IR
(class instruction). In DAG stage, the instructions are reordered, so I cannot
map the metadata to correct instruction if I cannot access instruction from DAG
or MachineInstr structure.

> On Nov 26, 2017, at 11:02 PM, Ryan Taylor <ryta1203 at gmail.com>
wrote:
> 
> It might be a more useful to know what it is you need from the IR in the
DAG or what it is you r trying to do?
> 
> 
> 
> On Nov 25, 2017 7:59 PM, "Jonathan via llvm-dev" <llvm-dev at
lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
> The llvm backend uses class Instruction in IR handle stage, create SDVaule
and DAG in DAG translation stage and class MachineInstr in Machine instruction
translation stage.
> Can I access class Instruction from DAG structure or stage, or access DAG
and Instruction from MachineInstr structure or stage?
> 
> Jonathan
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
<http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev>
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