Displaying 20 results from an estimated 4000 matches similar to: "Re: how hard it would be to implement a flac-decoder in VHDL"
2008 Jan 22
1
Implementing a flac-decoder in VHDL
Hello,
my name is Axel Reimer and I am new to this mailing list. I subscribed
because I was just thinking about how hard it would be to implement a
flac-decoder in VHDL (in order to use it on a Xilinx-FPGA).
Since I am working at a University in Germany I was thinking of offering
this project for students.
What do you think. How much time would you suggest for such an
implementation (if only
2008 Jan 22
0
Re: Implementing a flac-decoder in VHDL
Hello Axel,
I'm an undergraduate student who has been working on a student project
implementing a project like this for our Fourth Year Design Symposium (http://eceprojects.uwaterloo.ca
).
Our VHDL decoder is targeting an Altera FPGA (Cyclone II), however I
think that much of this would hold for your students project as well.
The project took significantly longer to complete than we
2011 Oct 06
0
[LLVMdev] LLVM and VHDL simulation
On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote:
> Hi,
>
> I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
> To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis
2011 Oct 07
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
Hi Jonas,
>Thanks for your answers.
>
>In one year, I am going to have something like a semester project.
>The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the
2014 Sep 02
2
[LLVMdev] Python to VHDL using LLVM; was "Re: LLVMdev Digest, Vol 123, Issue 3"
The only VHDL to LLVM project that I know of is nvc. [0] I haven't
tried it personally and from a cursory look through the source it
seems like there is a LLVM backend and a "native" backend (not sure
what that means). If you're really crazy you might want to see if you
could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM
backend for GCC) to get you LLVM IR.
I'm
2011 Oct 06
0
[LLVMdev] TR : LLVM and VHDL simulation
Thanks for your answers.
In one year, I am going to have something like a semester project.
The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL
2011 Oct 02
7
[LLVMdev] LLVM and VHDL simulation
Hi,
I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This
2011 Oct 10
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
Hi Pavel,
> If you are interested in HDLs perhaps you would be interested in Vlang?
> I am currently working on Verilog fronted and I am looking for somebody with
> VHDL interest to join the Vlang project.
I have never heard about the Vlang project but it seems to be an interesting project. I think I
could be interested to join this project and do the VHDL front-end.
However, there are
2012 Dec 04
1
[LLVMdev] VHDL to promela
To All,
Has anyone worked with generating vhdl code to promela script for the spin model checker??
David Blubaugh
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2004 Sep 10
1
VHDL Implementation?
I'm currently looking to start my working on my major project for
College. I want to create an audio CD archival/ playback server. There
will be a base server and also several satellite players. I will be
building a secondary server for my car. And in the car power is at a
premium so I wanted true hardware support (unlike phatnoise which is
software based). The car will support both
2011 Oct 02
0
[LLVMdev] LLVM and VHDL simulation
I don't have a solution for you, but when you found one or start the project
on your own, let me know.
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2008 Feb 07
0
Hardware FLAC decoder
I'd like to announce the first public demo of a hardware FLAC decoder
that I and three of my colleagues have been working on over the past 8
months. This project has been developed as part of the University of
Waterloo's Fourth Year Design Project requirement for undergrad
students in Electrical & Computer Engineering.
Our decoder has been implemented in VHDL and is currently
2002 Jul 17
1
Question on "root pivot" function
Seth,
Thank you for your reply. I'm sorry to bother with this, but what is
the "root pivot" function and
where can I find doc's on it.
From what I understand from your email the system would basically boot
twice. Once from a stripped
kernel on the floppy disk to mount the CD, and then after the CD is
mounted it would reboot with the
kernel and initial randisk found on the
2008 May 14
0
NFS subdirectory on client is out of sync
Today a user asked me whether a file on one host can be different on
another host. I was busy composing an answer to tell that the /home
space on all clients are mounted using NFS from the file server. Any
host will therefor see the same file. The user pointed me to his file
and I copied this file from the client and compared this with the file
on the file server. To my surprise it turned out
2013 Feb 09
2
Performance issue
Hi,
I suspect a CPU bottleneck in one of our PostgreSQL servers but not sure
how to confirm the suspect.
It's a DELL Box running CentOS 5.4 with 64GB RAM and 16 XEON E7430 2.13 GHz
processors. vmstat r column "run queue" usually indicates values higher
than 2 and less than 5 but "Load Average" values from top, sar -q and other
commands show always values less than 1.
2005 Feb 18
1
wikki problem
I'm trying to post a script on the wikki but it keeps screwing up the
text because it interprets the text as commands that cause graphical
errors.
Is there some trick to make the wiki think that the text is just text?
Tia,
Dean
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2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
A simulator should be expecting the machine opcodes not macros. LD shouldn't care at all as long as the object format plays well.
I would think it would be better to fix the simulator.
Jack
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From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] on behalf of llvmdev-request at cs.uiuc.edu [llvmdev-request at cs.uiuc.edu]
Sent: Thursday,
2013 Aug 30
2
[LLVMdev] Reflexions about a new HDL language
Hello,
I previously sent this message, but it was in HTML only, so it was
unreadable.
I am thinking about making a compiler for a new HDL language, that will
be more modern than VHDL and Verilog and allow a little higher level
behavioral description than VHDL. For this language, I am beeing
influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it
in Ada.
I don't know if it
2008 Jun 02
2
[LLVMdev] want to use CallGraph Pass in llc
Hi all,
the CallGraph pass is only available in opt. Is there any substantial reason
for that? Or is it only because it seems not to be useful for llc?
I want to use it in an backend that is derived from the CBackend. I need the
information what functions are called in every other function to build
communication struktures between the functions. The backend is generating
VHDL from C code.
2006 Apr 13
4
equivilent to PHP''s nl2br?
Hey all, this is a pretty simple question but I can''t seem to find
anything on the wikki or google... Is there a Ruby/Rails equivilent to
PHP''s nl2br function?
--
Posted via http://www.ruby-forum.com/.