similar to: [LLVMdev] Sequence of BuildMI without order dependency

On 03/22/2018 09:29 AM, Julius Hiller via llvm-dev wrote: > Hello everyone, > > I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. > To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. > I started with

Thank you for your help Tom you are totally right with the registers but the command you suggest also doesn't work. After some research I found the following thread on the mailing list: http://lists.llvm.org/pipermail/llvm-dev/2017-February/110086.html With your help and the information about the condition codes I was able to resolve the error:         BuildMI(BB, BB.end(), DL,

Hello everyone, I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. I started with branch instructions:     const TargetMachine &TM = MF.getTarget();

Hi all, I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird. For an add, when I use BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm). if reg is R0 - R7, everything is fine: I would get something like adds r1, 4 But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get

Dear All, I am working on a x86 backend machineFunction pass, where I am trying to save the hard coded address of an arbitrary machine basic block to memory in ASM. I know the assembly needed for this but am lost at how to construct the BuildMI(). Note that these machine basic blocks are not entry's to a function. but in the middle of the function. so using addGlobalAddress or

Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2. It has 12 regular registers (R0 - R12), and R8 - R12 are used. I can generate mov instruction that from/ R8-R12 to/from R0-R6. From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot use them

Dear there, I'm trying to call BuildMI in my backend to add a machineinstr. BuildMI(MBB, I, I->getDebugLoc(), TII->get(Vanilla::MOV), Vanilla::R1).addReg(MI->getOperand(1).getReg()); But it gives me an error like this: 0 clang 0x000000010e61a56e llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 46 1 clang 0x000000010e61c209

Hi Craig, Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7? I tried to search in ARMInstrThumb.td but couldn’t find it. Thanks, - Jie On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote: I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2

Why do these two guys take a pointer to the basic block, whereas all other BuildMI functions take a reference? They are not checking for null or anything and I didn't see any potential declaration conflicts. Am I missing something? Is there a reason for this? inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL,

Hello everyone, I'm a newbie of llvm. I'm trying to insert Intel MPX instruction BNDCU with BuildMI. I add my machinefunctionpass at addPreEmitPass2. Here is the code of insertion: BuildMI(MBB, MI, DL, TII->get(X86::BNDCU64rr)).addReg(X86::BND2, RegState::Define).addReg(X86::R10); And here is to stack track when I compiler program with modified llc:

Hi Bill, I am using the following version of BuildMI : MachineInstrBuilder BuildMI(MachineFunction &MF, const TargetInstrDesc &TID, unsigned DestReg) I do the following : void createInstrs(std::vector<MachineInstr *>& ilist) { Machine Instr *mi; mi = BuildMI(MF, someTID, somereg);

Dear Mr. Northover, Thank you for the quick reply. You are correct about the address-mode operands :) . I guess an important detail left out was that the basic block (call it A) that wants to calculate the address of the target stationary trampoline basic block (call it B) will be moved around in memory during run-time. Our earlier solution, before the feature was implemented to move around (A)

Hi all, While I using BuildMI with MachineBasicBlock as parameter, I made a mistake. The mistake was that the MachineBasicBlock of instruction, which is for insertion, is different with given MachineBasicBlock as parameter. I have thought if there is assertion code to check whether MachineBasicBlocks are same between instruction's MachineBasicBlock and given MachineBasicBlock as

Hi LLVM Dev, I have an old problem that I've wanted to clean-up for some time. Our chip has gone through a number of iterations in the past few years, but with each revision there have been changes to some of the mnemonics for instructions. These are mostly very simple, for example we had a 32-bit load from memory instruction named 'LD32' in one version of the chip, but for a

Hi Stephen, > I'm not entirely sure what is wrong here - I assume it has something to do > with my 'special' instruction LDri_ab. This instruction is a load with an > 'address writeback' - ld.ab r0, [r1, 5] is equivalent to ld r0, [r1]; add > r1, r1, 5. As it was very difficult to match such behaviour automatically, I > actually only generate them manually for

It looks like you are not using the right overloaded version of function BuildMI defined in MachineInstrBuilder.h. The register operand added to instruction sb should be a use, not a def operand. So this function should be called, BuildMI(BB, dl, TII->get(Mips::SB)).addReg(tmpReg1) instead of BuildMI(BB, dl, TII->get(Mips::SB), tmpReg1) On Sat, Jul 21, 2012 at 11:41 AM, Yang Yang

Hi, I'm having trouble using virtual register in the X86 backend. I implemented a new intrinsic and I use a custom inserter. The goal of the intrinsic is to set the content of the stack to zero at the end of each function. Here is my code: MachineBasicBlock * X86TargetLowering::EmitBURNSTACKWithCustomInserter( MachineInstr *MI, MachineBasicBlock

Hi all, I am really stumped on a problem for long. I could not figure out why. That is why i am here. OK, here is the problem: I tried to insert a MachineBasicBlock into a function. Here is the code snippet: // insert a machine basic block with the error_label into MF and before I // Pred is the predecessor of the block to be inserted // the new basic block is inserted right before I void

Hi Evan, Evan Cheng wrote: > The patch looks great. But I do have one comment: > > +let usesCustomDAGSchedInserter = 1 in { > + let Uses = [CR0] in { > + let Uses = [R0] in > + def ATOMIC_LOAD_ADD_I32 : Pseudo< > > The "let Uses = [R0]" is not needed. The pseudo instruction will be > expanded like this later: > > + BuildMI(BB,

Reed, Couldn't you also use instruction scheduling classes and specify that the second instruction has a bypass from the first instruction? The scheduler should always schedule them together in that case. Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of reed kotler > Sent: Tuesday, September 17, 2013