similar to: [LLVMdev] How to use property 'isCommutable' in target description file?

Hello > How can i tell the system X=A*B + C == X = B*A + C == X=C+A*B == X=C+B*A by > property 'isCommutable'? Is it necessary to do that? Most probably you will need to write a special hook to commute this instruction. However, everything depends on your target (e.g. if there is an output register tied to one of the input). > *** Another question: Why set isCommutable = 1 in

Thanks to Anton. Frankly said i don't know the exact meaning and purpose of 'isCommutable'. By my opinion "add.w r6, r7" != "add.w r7, r6", so we shouldn't set isCommutable = 1. Who would like give an example to demonstrate what benifit it has if 'isCommuatble=1' in instruction selection, register allocation or other process? Regards 2009/12/7,

Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects =

Hi, 1. This instruction is not selected automatically by the instruction selector. The instruction combine / select stages insert registercopies, and they are expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo to this MOV16rr. 2. ReMaterializable means there is no need to find a way to preserve the value in a register : the instruction can be just be reissued

Evan Cheng wrote: > On Apr 16, 2009, at 3:17 PM, Greg McGary wrote: > >> Is there some optimizer knob I'm not turning properly? In more complex >> cases, GCC does poorly with two-address operand choices and so bloats >> the code with unnecessary register moves. I have high hopes LLVM >> can do better, so this result for a simple case is bothersome. >>

This variant works: class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx,

I think that what I did originally should have worked and the bug was correct as I reported it. Here is an alternate implementation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList,

hi, at the moment, TEST instruction is defined with 0xf7 opcode, as demonstrated below. $ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86 .section __TEXT,__text,regular,pure_instructions testl $570425344, %eax ## imm = 0x22000000 however, i cannot find anywhere this F7 opcode is defined in

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the

Hi Chris, Thanks a lot for your answer! Chris Lattner wrote: >> 1. Why does X86 instruction set description provide different >> descriptions for the same instructions, which differ only in the size >> of operands? >> E.g. >> >> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), >> "mov{b} {$src, $dst|$dst, $src}",

I've filed the following bug. Maybe I'm doing something stupid here or maybe someone knows of a workaround. The following fragment from mips16 (not yet checked into main source). The problem is that I should be able to pass parameters: I.OutOperandList, I.InOperandList But instead, I must back substitute what I know the values of these are. (outs CPU16Regs:$rx), (ins CPU16Regs:$ry,

Not sure what you mean. I.OutOperandList == (outs CPU16Regs:$rx) I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) On 07/02/2012 09:26 PM, Sean Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args though... which makes me wonder what is

class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : // ... This class has template args. You don't specify them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote: > Not sure what you mean.

Sure I will split it and put it in two patches. Give me few hours. I need to test those patches. Sirish On 4/19/2012 8:40 AM, Tom Stellard wrote: > On Wed, Apr 18, 2012 at 11:18:05PM -0500, Sirish Pande wrote: >> Hi, >> >> Here's a patch for Hexagon Packetizer for review. This patch does >> not yield any warnings. >> > Would it be possible to split this

Hi All, I am working on writing pass in LLVM and interested in doing function permutation at intermediate representation byte code level? If I have lets say C program having three functions and its corresponding IR bytecode. void findLen(char a[10]) { int tmp = strlen(a); printf("Len is : %d\n", tmp); } void muladd(int a, int b, int c) { int tmp = a + b; int tmp1 = tmp *

Hi everyone, I try to add an instruction to x86. The instruction is a multiply-add instruction MULADD A, B, C; //A = A + B * C. I use the instruction by inline assemble as below int x, y, z; ..... .... x = 0; asm("MULADD %0, %1, %2":"=r"(x):"0"(x), "r"(y), "r"(z)); ..... .... The backend does allocate registers %edx, %edi, %esi for x,y, z

all subexpression inside an ir_assignment needs to be tagged as precise. Signed-off-by: Karol Herbst <karolherbst at gmail.com> --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 80 ++++++++++++++++++++++++------ 1 file changed, 65 insertions(+), 15 deletions(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index c5d2e0fcd2..19f90f21fe

Hi,every one. I' in trouble again. I want add a new intrinsic mapping a new instruction. I add the int_x86_max_qb as fllowing: def int_x86_max_qb: GCCBuiltin<"__builtin_x86_max_qb">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [Commutative]>; BUILTIN(__builtin_x86_max_qb, "iii", "") I define the intrinsic as Pseudo instruction,it

On 8 November 2012 11:12, Cameron McInally <cameron.mcinally at nyu.edu> wrote: > On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com> > wrote: > ... >> >> For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and >> "MemOp4" like those of "rm" or "rr" ? >

On Dec 29, 2009, at 3:09 AM, Heyu Zhu wrote: > Hi everyone, > > I try to add an instruction to x86. The instruction is a multiply-add instruction > MULADD A, B, C; //A = A + B * C. > I use the instruction by inline assemble as below > > int x, y, z; > ..... .... > x = 0; > asm("MULADD %0, %1, %2":"=r"(x):"0"(x), "r"(y),