thr3ads.net - llvm dev - [LLVMdev] where is F7 opcode for TEST instruction on X86? [Apr 2014]

If this information is useful, please help other people find it:
Share via:

Jun Koi

2014-Apr-22 13:45 UTC

[LLVMdev] where is F7 opcode for TEST instruction on X86?

hi,

at the moment, TEST instruction is defined with 0xf7 opcode, as
demonstrated below.

$ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc
-disassemble -arch=x86
    .section    __TEXT,__text,regular,pure_instructions
    testl    $570425344, %eax        ## imm = 0x22000000

however, i cannot find anywhere this F7 opcode is defined in
lib/Target/X86/X86InstrArithmetic.td.
we only have TEST defined with F6 & other opcode like below.

any hint please?

thanks.


let isCompare = 1 in {
  let Defs = [EFLAGS] in {
    let isCommutable = 1 in {
      def TEST8rr  : BinOpRR_F<0x84, "test", Xi8 , X86testpat,
MRMSrcReg>;
      def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat,
MRMSrcReg>;
      def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat,
MRMSrcReg>;
      def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat,
MRMSrcReg>;
    } // isCommutable

    def TEST8rm    : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
    def TEST16rm   : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
    def TEST32rm   : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
    def TEST64rm   : BinOpRM_F<0x84, "test", Xi64, X86testpat>;

    def TEST8ri    : BinOpRI_F<0xF6, "test", Xi8 , X86testpat,
MRM0r>;
    def TEST16ri   : BinOpRI_F<0xF6, "test", Xi16, X86testpat,
MRM0r>;
    def TEST32ri   : BinOpRI_F<0xF6, "test", Xi32, X86testpat,
MRM0r>;
    def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat,
MRM0r>;

    def TEST8mi    : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m,
0xF6>;
    def TEST16mi   : BinOpMI_F<"test", Xi16, X86testpat, MRM0m,
0xF6>;
    def TEST32mi   : BinOpMI_F<"test", Xi32, X86testpat, MRM0m,
0xF6>;
    def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m,
0xF6>;

    // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
    // register class is constrained to GR8_NOREX.
    let isPseudo = 1 in
    def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src,
i8imm:$mask),
                          "", [], IIC_BIN_NONMEM>,
Sched<[WriteALU]>;
  } // Defs = [EFLAGS]

  def TEST8i8    : BinOpAI<0xA8, "test", Xi8 , AL,
                           "{$src, %al|al, $src}">;
  def TEST16i16  : BinOpAI<0xA8, "test", Xi16, AX,
                           "{$src, %ax|ax, $src}">;
  def TEST32i32  : BinOpAI<0xA8, "test", Xi32, EAX,
                           "{$src, %eax|eax, $src}">;
  def TEST64i32  : BinOpAI<0xA8, "test", Xi64, RAX,
                           "{$src, %rax|rax, $src}">;
} // isCompare
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20140422/8069588a/attachment.html>

Craig Topper

2014-Apr-22 15:39 UTC

head link

[LLVMdev] where is F7 opcode for TEST instruction on X86?

If memory serves the Xi16, Xi32, and Xi64 types cause some magic inside of
BinOpMI_F(or classes it inherits from) to OR a 1 into the LSB of the opcode.


On Tue, Apr 22, 2014 at 6:45 AM, Jun Koi <junkoi2004 at gmail.com> wrote:
> hi,
>
> at the moment, TEST instruction is defined with 0xf7 opcode, as
> demonstrated below.
>
> $ echo "0xf7 0xc0 0x00 0x00 0x00
0x22"|./Release+Asserts/bin/llvm-mc
> -disassemble -arch=x86
>     .section    __TEXT,__text,regular,pure_instructions
>     testl    $570425344, %eax        ## imm = 0x22000000
>
> however, i cannot find anywhere this F7 opcode is defined in
> lib/Target/X86/X86InstrArithmetic.td.
> we only have TEST defined with F6 & other opcode like below.
>
> any hint please?
>
> thanks.
>
>
> let isCompare = 1 in {
>   let Defs = [EFLAGS] in {
>     let isCommutable = 1 in {
>       def TEST8rr  : BinOpRR_F<0x84, "test", Xi8 , X86testpat,
MRMSrcReg>;
>       def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat,
MRMSrcReg>;
>       def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat,
MRMSrcReg>;
>       def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat,
MRMSrcReg>;
>     } // isCommutable
>
>     def TEST8rm    : BinOpRM_F<0x84, "test", Xi8 ,
X86testpat>;
>     def TEST16rm   : BinOpRM_F<0x84, "test", Xi16,
X86testpat>;
>     def TEST32rm   : BinOpRM_F<0x84, "test", Xi32,
X86testpat>;
>     def TEST64rm   : BinOpRM_F<0x84, "test", Xi64,
X86testpat>;
>
>     def TEST8ri    : BinOpRI_F<0xF6, "test", Xi8 , X86testpat,
MRM0r>;
>     def TEST16ri   : BinOpRI_F<0xF6, "test", Xi16, X86testpat,
MRM0r>;
>     def TEST32ri   : BinOpRI_F<0xF6, "test", Xi32, X86testpat,
MRM0r>;
>     def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat,
MRM0r>;
>
>     def TEST8mi    : BinOpMI_F<"test", Xi8 , X86testpat,
MRM0m, 0xF6>;
>     def TEST16mi   : BinOpMI_F<"test", Xi16, X86testpat,
MRM0m, 0xF6>;
>     def TEST32mi   : BinOpMI_F<"test", Xi32, X86testpat,
MRM0m, 0xF6>;
>     def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat,
MRM0m, 0xF6>;
>
>     // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
>     // register class is constrained to GR8_NOREX.
>     let isPseudo = 1 in
>     def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src,
> i8imm:$mask),
>                           "", [], IIC_BIN_NONMEM>,
Sched<[WriteALU]>;
>   } // Defs = [EFLAGS]
>
>   def TEST8i8    : BinOpAI<0xA8, "test", Xi8 , AL,
>                            "{$src, %al|al, $src}">;
>   def TEST16i16  : BinOpAI<0xA8, "test", Xi16, AX,
>                            "{$src, %ax|ax, $src}">;
>   def TEST32i32  : BinOpAI<0xA8, "test", Xi32, EAX,
>                            "{$src, %eax|eax, $src}">;
>   def TEST64i32  : BinOpAI<0xA8, "test", Xi64, RAX,
>                            "{$src, %rax|rax, $src}">;
> } // isCompare
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
>

-- 
~Craig
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20140422/f63485ea/attachment.html>

Jun Koi

2014-Apr-24 03:25 UTC

head link

[LLVMdev] where is F7 opcode for TEST instruction on X86?

On Tue, Apr 22, 2014 at 11:39 PM, Craig Topper <craig.topper at
gmail.com>wrote:
> If memory serves the Xi16, Xi32, and Xi64 types cause some magic inside of
> BinOpMI_F(or classes it inherits from) to OR a 1 into the LSB of the
opcode.
>
>Thanks a lot, Craig!




>
> On Tue, Apr 22, 2014 at 6:45 AM, Jun Koi <junkoi2004 at gmail.com>
wrote:
>
>>  hi,
>>
>> at the moment, TEST instruction is defined with 0xf7 opcode, as
>> demonstrated below.
>>
>> $ echo "0xf7 0xc0 0x00 0x00 0x00
0x22"|./Release+Asserts/bin/llvm-mc
>> -disassemble -arch=x86
>>     .section    __TEXT,__text,regular,pure_instructions
>>     testl    $570425344, %eax        ## imm = 0x22000000
>>
>> however, i cannot find anywhere this F7 opcode is defined in
>> lib/Target/X86/X86InstrArithmetic.td.
>> we only have TEST defined with F6 & other opcode like below.
>>
>> any hint please?
>>
>> thanks.
>>
>>
>> let isCompare = 1 in {
>>   let Defs = [EFLAGS] in {
>>     let isCommutable = 1 in {
>>       def TEST8rr  : BinOpRR_F<0x84, "test", Xi8 ,
X86testpat, MRMSrcReg>;
>>       def TEST16rr : BinOpRR_F<0x84, "test", Xi16,
X86testpat, MRMSrcReg>;
>>       def TEST32rr : BinOpRR_F<0x84, "test", Xi32,
X86testpat, MRMSrcReg>;
>>       def TEST64rr : BinOpRR_F<0x84, "test", Xi64,
X86testpat, MRMSrcReg>;
>>     } // isCommutable
>>
>>     def TEST8rm    : BinOpRM_F<0x84, "test", Xi8 ,
X86testpat>;
>>     def TEST16rm   : BinOpRM_F<0x84, "test", Xi16,
X86testpat>;
>>     def TEST32rm   : BinOpRM_F<0x84, "test", Xi32,
X86testpat>;
>>     def TEST64rm   : BinOpRM_F<0x84, "test", Xi64,
X86testpat>;
>>
>>     def TEST8ri    : BinOpRI_F<0xF6, "test", Xi8 ,
X86testpat, MRM0r>;
>>     def TEST16ri   : BinOpRI_F<0xF6, "test", Xi16,
X86testpat, MRM0r>;
>>     def TEST32ri   : BinOpRI_F<0xF6, "test", Xi32,
X86testpat, MRM0r>;
>>     def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64,
X86testpat, MRM0r>;
>>
>>     def TEST8mi    : BinOpMI_F<"test", Xi8 , X86testpat,
MRM0m, 0xF6>;
>>     def TEST16mi   : BinOpMI_F<"test", Xi16, X86testpat,
MRM0m, 0xF6>;
>>     def TEST32mi   : BinOpMI_F<"test", Xi32, X86testpat,
MRM0m, 0xF6>;
>>     def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat,
MRM0m, 0xF6>;
>>
>>     // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure
>> the
>>     // register class is constrained to GR8_NOREX.
>>     let isPseudo = 1 in
>>     def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src,
>> i8imm:$mask),
>>                           "", [], IIC_BIN_NONMEM>,
Sched<[WriteALU]>;
>>   } // Defs = [EFLAGS]
>>
>>   def TEST8i8    : BinOpAI<0xA8, "test", Xi8 , AL,
>>                            "{$src, %al|al, $src}">;
>>   def TEST16i16  : BinOpAI<0xA8, "test", Xi16, AX,
>>                            "{$src, %ax|ax, $src}">;
>>   def TEST32i32  : BinOpAI<0xA8, "test", Xi32, EAX,
>>                            "{$src, %eax|eax, $src}">;
>>   def TEST64i32  : BinOpAI<0xA8, "test", Xi64, RAX,
>>                            "{$src, %rax|rax, $src}">;
>> } // isCompare
>>
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>>
>
>
> --
> ~Craig
>-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20140424/3268855e/attachment.html>

Apparently Analagous Threads

Search for more seemingly similar threads

llvm dev - Apr 2014 - [LLVMdev] where is F7 opcode for TEST instruction on X86?

[LLVMdev] where is F7 opcode for TEST instruction on X86?

[LLVMdev] where is F7 opcode for TEST instruction on X86?

[LLVMdev] where is F7 opcode for TEST instruction on X86?

Apparently Analagous Threads