llvm dev - Dec 2011 - [LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading

Hi all. The question about 'load' instruction.
When we promote
v2i5 = load <addr> ; <MemoryVT = v2i5>
to
v2i64 = load <addr> ;<MemoryVT = v2i5>

should we insert vector shuffling that moves second v2i5 item to the 
second v2i64 item?

Or it is still depends from target?

Thanks.

-Stepan.

Hi Stepan, it was never really decided how to represent v2i5 in memory
(bitpacked?), and the code generators just don't support it right now.
> Hi all. The question about 'load' instruction.
> When we promote
> v2i5 = load<addr>  ;<MemoryVT = v2i5>
> to
> v2i64 = load<addr>  ;<MemoryVT = v2i5>
>
> should we insert vector shuffling that moves second v2i5 item to the
> second v2i64 item?
This question doesn't make any sense to me.  The operation should result
in the first i5 being in the low 5 bits of the first i64, and the second
i5 being in the low 5 bits of the second i64.  That's the definition of
this extending load operation.  Talking about shuffling only makes sense
in terms of a particular implementation of this operation, and I'm not
sure what you have in mind.

Ciao, Duncan.
>
> Or it is still depends from target?
>
> Thanks.
>
> -Stepan.
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

Probably, I misunderstood MemoryVT purpose? Should it be a type that 
equal to original vector type (e.g. v2i5). Or it is a type of memory 
area for this vector (e.g. v2i8) ?

-Stepan.

Stepan Dyatkovskiy wrote:
> Hi all. The question about 'load' instruction.
> When we promote
> v2i5 = load<addr>  ;<MemoryVT = v2i5>
> to
> v2i64 = load<addr>  ;<MemoryVT = v2i5>
>
> should we insert vector shuffling that moves second v2i5 item to the
> second v2i64 item?
>
> Or it is still depends from target?
>
> Thanks.
>
> -Stepan.
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

Yes. It doesn't works properly. I also read the your discussion in bug 
1784: http://llvm.org/bugs/show_bug.cgi?id=1784
I found that know Type and Vector Lagalization and in DAGCombining 
implicitly assumed that element size of MemoryVT is multiply of 8 bits. 
Thats the main reason why v2i5 works improperly with load/store. But I 
can't determine exactly what MemoryVT means...

-Stepan.

Stepan Dyatkovskiy wrote:
> Probably, I misunderstood MemoryVT purpose? Should it be a type that
> equal to original vector type (e.g. v2i5). Or it is a type of memory
> area for this vector (e.g. v2i8) ?
>
> -Stepan.
>
> Stepan Dyatkovskiy wrote:
>> Hi all. The question about 'load' instruction.
>> When we promote
>> v2i5 = load<addr>   ;<MemoryVT = v2i5>
>> to
>> v2i64 = load<addr>   ;<MemoryVT = v2i5>
>>
>> should we insert vector shuffling that moves second v2i5 item to the
>> second v2i64 item?
>>
>> Or it is still depends from target?
>>
>> Thanks.
>>
>> -Stepan.
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev