search for: push

...-------------------- > 4 files changed, 93 insertions(+), 63 deletions(-) > > diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c > index 0682806..8da5051 100644 > --- a/src/nvc0_accel.c > +++ b/src/nvc0_accel.c > @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) > PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); > PUSH_DATA (push, (bo->offset + MISC_OFFSET)); > PUSH_DATA (push, 1); > + } else { > + /* Use new TIC format. Not strictly necessary for GM20x+ */ Yes, but it's also enabled by default in mesa, looks fine. > +...

...--- src/nvc0_accel.c | 4 ++-- src/nvc0_exa.c | 2 +- 10 files changed, 33 insertions(+), 32 deletions(-) diff --git a/src/nv10_exa.c b/src/nv10_exa.c index 78bc739..7daa281 100644 --- a/src/nv10_exa.c +++ b/src/nv10_exa.c @@ -697,9 +697,9 @@ NVAccelInitNV10TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0); } - BEGIN_NV04(push, SUBC_3D(0x290), 1); + BEGIN_NV04(push, NV10_3D(UNK0290), 1); PUSH_DATA (push, (0x10<<16)|1); - BEGIN_NV04(push, SUBC_3D(0x3f4), 1); + BEGIN_NV04(push, NV10_3D(UNK03F4), 1); PUSH_DATA (push, 0); BEGIN_NV04(push, NV04_GRAPH(3D, NOP), 1); @@ -707,...

...-------------------- > 4 files changed, 93 insertions(+), 64 deletions(-) > > diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c > index 0682806..8da5051 100644 > --- a/src/nvc0_accel.c > +++ b/src/nvc0_accel.c > @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) > PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); > PUSH_DATA (push, (bo->offset + MISC_OFFSET)); > PUSH_DATA (push, 1); > + } else { > + /* Use new TIC format. Not strictly necessary for GM20x+ */ > + IMMED_NVC0(push, SUBC_3D(0x0f10), 1); > + if (pNv->dev-&gt...

...67 +++++++++++++++++++------------------------------------- 4 files changed, 93 insertions(+), 63 deletions(-) diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c index 0682806..8da5051 100644 --- a/src/nvc0_accel.c +++ b/src/nvc0_accel.c @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); PUSH_DATA (push, (bo->offset + MISC_OFFSET)); PUSH_DATA (push, 1); + } else { + /* Use new TIC format. Not strictly necessary for GM20x+ */ + IMMED_NVC0(push, SUBC_3D(0x0f10), 1); + if (pNv->dev->chipset >= 0x120) { + /*...

...67 +++++++++++++++++++------------------------------------- 4 files changed, 93 insertions(+), 64 deletions(-) diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c index 0682806..8da5051 100644 --- a/src/nvc0_accel.c +++ b/src/nvc0_accel.c @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); PUSH_DATA (push, (bo->offset + MISC_OFFSET)); PUSH_DATA (push, 1); + } else { + /* Use new TIC format. Not strictly necessary for GM20x+ */ + IMMED_NVC0(push, SUBC_3D(0x0f10), 1); + if (pNv->dev->chipset >= 0x120) { + /*...

...d, 93 insertions(+), 63 deletions(-) >> >> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c >> index 0682806..8da5051 100644 >> --- a/src/nvc0_accel.c >> +++ b/src/nvc0_accel.c >> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) >> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); >> PUSH_DATA (push, (bo->offset + MISC_OFFSET)); >> PUSH_DATA (push, 1); >> + } else { >> + /* Use new TIC format. Not strictly necessary for GM20x+ >> */ &gt...

We still have to push everything out, might as well kick earlier and flip pushbufs when we know we'll need it. This resolves some issues with the new policy of making sure that we always leave a bit of room at the end for fences. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: mesa-stable at lists.fr...

...t a/src/gallium/drivers/nouveau/nv50/nv50_context.h b/src/gallium/drivers/nouveau/nv50/nv50_context.h index 57a3090..84ff46e 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_context.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_context.h @@ -173,6 +173,8 @@ struct nv50_context { boolean vbo_push_hint; + uint32_t rt_array_mode; + struct pipe_query *cond_query; boolean cond_cond; uint cond_mode; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c index f953422..100d02d 100644 --- a/src/gallium/drivers/no...

This patch-series implements the ARB_viewport_array for nvc0 and does a little house-cleanig afterwords. Tobias Klausmann (3): nvc0: implement multiple viewports/scissors, enable ARB_viewport_array nvc0: mark scissor in nvc0_clear_{} nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer .../drivers/nouveau/codegen/nv50_ir_driver.h | 1 -

Hi, please review the following patch! Thanks, Tobias Klausmann

...p(pipe, pt); +} + +static void +nvc0_clear_buffer(struct pipe_context *pipe, + struct pipe_resource *res, + unsigned offset, unsigned size, + const void *data, int data_size) +{ + struct nvc0_context *nvc0 = nvc0_context(pipe); + struct nouveau_pushbuf *push = nvc0->base.pushbuf; + struct nv04_resource *buf = nv04_resource(res); + union pipe_color_union color; + enum pipe_format dst_fmt; + unsigned width, height, elements; + + assert(res->target == PIPE_BUFFER); + assert(nouveau_bo_memtype(buf->bo) == 0); + + switch (dat...

..._display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -791,6 +791,23 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) } static int +nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec) +{ + struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); + u32 *push; + + push = evo_wait(mast, 8); + if (!push) + return -ENOMEM; + + evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1); + evo_data(push, usec); + evo_kick(push, mast); + + return 0; +} + +static int nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) { struct nv50_mast *...

This patch-series implements the ARB_viewport_array for nvc0 and does a little house-cleanig afterwords. V2: Add Release-Notes, mark this in GL3 as done for nvc0 Don't mark the scissors dirty when we don't need to do that Tobias Klausmann (3): nvc0: implement multiple viewports/scissors, enable ARB_viewport_array docs: update GL3.txt, relnotes: mark GL_ARB_viewport_array as done

...p(pipe, pt); +} + +static void +nvc0_clear_buffer(struct pipe_context *pipe, + struct pipe_resource *res, + unsigned offset, unsigned size, + const void *data, int data_size) +{ + struct nvc0_context *nvc0 = nvc0_context(pipe); + struct nouveau_pushbuf *push = nvc0->base.pushbuf; + struct nv04_resource *buf = nv04_resource(res); + union pipe_color_union color; + enum pipe_format dst_fmt; + unsigned width, height, elements; + + assert(res->target == PIPE_BUFFER); + assert(nouveau_bo_memtype(buf->bo) == 0); + + switch (dat...

..............^ +a A34D BB 0000 mov bx, # ***** factor expected.....................................^ +a A353 BB 0000 mov bx, # ***** factor expected.....................................^ +a A35B 68 0000 push # ***** factor expected..................................^ +a A360 68 0000 push # ***** factor expected..................................^ +a A36B 68 0000 push # ***** factor expected..................................^ +a A370...

.../nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c index 358f57a..eb27429 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c @@ -408,9 +408,6 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, PUSH_DATAf(push, color->f[1]); PUSH_DATAf(push, color->f[2]); PUSH_DATAf(push, color->f[3]); - mode = - NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G | - NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A; } if (buffers & PIPE_CLEAR_DEPTH) { @...

On Sat, Oct 10, 2015 at 3:41 PM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > This patch looks fine except that it should be a bit more normalized. I > mean, sometimes you break when PUSH_SPACE fails, sometimes not. Same for > PUSH_SPACE calls, sometimes you add it sometimes not. Meh. We need to get our error checking situation straight, but this isn't the patch to do it in. > > Did you run a full piglit test this time ? :) Nope, but I ran a full piglit before this p...

...return 0; case PIPE_CAP_MAX_VIEWPORTS: - return 1; + return NVC0_MAX_VIEWPORTS; case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_SAMPLE_SHADING: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: @@ -933,19 +933,23 @@ nvc0_screen_create(struct nouveau_device *dev) BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1); PUSH_DATA (push, 1); - BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2); - PUSH_DATAf(push, 0.0f); - PUSH_DATAf(push, 1.0f); + for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) { + BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2); + PUSH_DATAf(...

...d, 93 insertions(+), 64 deletions(-) >> >> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c >> index 0682806..8da5051 100644 >> --- a/src/nvc0_accel.c >> +++ b/src/nvc0_accel.c >> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) >> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); >> PUSH_DATA (push, (bo->offset + MISC_OFFSET)); >> PUSH_DATA (push, 1); >> + } else { >> + /* Use new TIC format. Not strictly necessary for GM20x+ >> */ &gt...

...c *nv_crtc, u32 usec) > > What's "dmi"? SetRasterVertBlankDmi is the name of method 0x828. I presume it's Display Memory Interface or something to that effect. > >> +{ >> + struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); >> + u32 *push; >> + >> + push = evo_wait(mast, 8); > > Just needs to be 2, no? Yes, doesn't matter too much though. > >> + if (!push) >> + return -ENOMEM; >> + >> + evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1); >>...