search for: s16imm

...PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register: class isDOT { list<Register> Defs = [CR0]; bit RC = 1; } and this gets used on instructions such as: def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic. $rD, $rA, $imm", IntGeneral, []>, isDOT; but there is a small problem. If these instructions are also part of a larger block which also defines registers, like this: let Defs = [CARRY] in def ADDICo : DForm_2<13, (outs GPRC:...

...class used to define instructions that implicitly define a condition register: > > class isDOT { > list<Register> Defs = [CR0]; > bit RC = 1; > } > > and this gets used on instructions such as: > > def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), > "addic. $rD, $rA, $imm", IntGeneral, > []>, isDOT; > > but there is a small problem. If these instructions are also part of a larger block which also defines registers, like this: > > let Defs = [CARRY] in > def AD...

...ne a condition register: > > > > class isDOT { > > list<Register> Defs = [CR0]; > > bit RC = 1; > > } > > > > and this gets used on instructions such as: > > > > def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, > > s16imm:$imm), > > "addic. $rD, $rA, $imm", IntGeneral, > > []>, isDOT; > > > > but there is a small problem. If these instructions are also part > > of a larger block which also defines registers, like this: > > &gt...

...peProfile<0, 3, [SDTCisSameAs<0, 1>]>; def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag, [SDNPOutGlue]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-0} = imm; let format = AFrm; let...

...quot;, SDT_EsenciaSetFlag, [SDNPOutGlue]>; def Esencia_CC_LT : PatLeaf<(imm), [{return (N->getZExtValue() == ISD::SETLT);}]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Esenciasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-0} = imm; let format = AFrm; le...

I've added a new register class to my target, but haven't used any of the new registers in any of the instructions. However when I compile llvm I get the following error: In SFEQ_ri: Could not infer all types in pattern Curiously all the instructions where this error occurs are the set flag instructions (flags like zero, less than, greater than etc). Would anyone be able to figure out

...LAG", SDT_EscalaSetFlag, [SDNPOutGlue]>; def Escala_CC_EQ : PatLeaf<(imm), [{return (N->getZExtValue() == ISD::SETEQ);}]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-0} = imm; let format = AFrm; let...

On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote: > > def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; > > > I think for setting an implicit register, you still need to have 1 result > here. > > If you look at

...), (i32 GPR:$rB), Cond)]> { bits<5> op2; bits<5> rA; bits<5> rB; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-11} = rB; let op2 = op2Val; } class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-0} = imm; let format = AFrm; let...

...$ptr))]>; -def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label), - "cmpd $rA, $rB\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>; -def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label), - "cmpdi $rA, $imm\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>; -} +let Defs = [CR0] in +def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), +...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...$ptr))]>; -def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label), - "cmpd $rA, $rB\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>; -def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label), - "cmpdi $rA, $imm\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>; -} +let Defs = [CR0] in +def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), +...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...$ptr))]>; -def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label), - "cmpd $rA, $rB\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>; -def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label), - "cmpdi $rA, $imm\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>; -} +let Defs = [CR0] in +def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), +...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...$ptr))]>; -def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label), - "cmpd $rA, $rB\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, G8RC:$rB, imm:$label)]>; -def CMP_UNRESdi : Pseudo<(outs), (ins G8RC:$rA, s16imm64:$imm, i32imm:$label), - "cmpdi $rA, $imm\n\tbne- La${label}_exit", - [(PPCcmp_unres G8RC:$rA, immSExt16:$imm, imm:$label)]>; -} +let Defs = [CR0] in +def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), +...