search for: i16imm

...d assigned :OR with 2" will not work. I suspect that llc is assuming that HL will contain 8 (that's the start) and or-ing 8 with 1 or with 2 is ok. But my HL has also added SP to it. This is how my ISD::FrameIndex instruction look like: def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src), "ld $dst, $disp\n\tadd $dst,$src", [(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>; So it say that HL16:$dst wich is only HL register, will be changed. I also tried to change it to <(outs HL16:$dst), (ins i16imm:$disp, SP16:$src), But the output is the...

...ecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, >>>> Constant:i16<127> >>>> >>>> In the instruction selection phase, what pattern would that match? I've >>>> constructed this so far: >>>> >>>> (??? REG16:$dst, i16imm:$src) >>>> >>>> but the problem is, I can't determine what to use as ???. There is an >>>> ISD::CopyToReg enum value, but I don't know how that translates to the >>>> string to use in the pattern. >>>> >>>> And more gen...

...h opcode: Opcode Instruction node pattern 0x46 LD $dst,(HL) (set GR8:$dst, (load HL)) 0x0A LD A,(BC) (set A, (load BC)) 0x1A LD A,(DE) (set A, (load DE)) 0x3A LD A,($src) (set A, (load i16imm:$src)) Target Description file: ... let canFoldAsLoad = 1, isReMaterializable = 1 in { let Uses = [HL] in def LD8rm : IRy<0x46, (outs GR8:$dst), (ins), "ld\t{$dst, (hl)}", [(set GR8:$dst, (load HL))]>; let Defs = [A], Uses = [BC] in def LD8AmBC : I<0x0A, (outs),...

...> work. > > I suspect that llc is assuming that HL will contain 8 (that's the start) > and or-ing 8 with 1 or with 2 is ok. > But my HL has also added SP to it. > This is how my ISD::FrameIndex instruction look like: > > def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src), > "ld $dst, $disp\n\tadd $dst,$src", > [(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>; > > So it say that HL16:$dst wich is only HL register, will be changed. > I also tried to change it to > <(outs HL16:$dst), (ins i16imm:$disp, SP16:$sr...

I have two patterns in tablegen that do look like the exact same thing: Pat 1) def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst), (ins i16imm:$val), asm, [(set GPRV4I16:$dst, (build_vector (i16 imm:$val)))]>; Pat 2) def v4i16imm : Operand<v4i16>; def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst), (ins v4i16imm:$val), asm, [(set GPRV4I16:$dst, (v4i16 imm:$val))]>; The second pattern seems to buil...

So there's a DAG that looks like this in the debug output: Selecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, Constant:i16<127> In the instruction selection phase, what pattern would that match? I've constructed this so far: (??? REG16:$dst, i16imm:$src) but the problem is, I can't determine what to use as ???. There is an ISD::CopyToReg enum value, but I don't know how that translates to the string to use in the pattern. And more generally, how do I find out from a DAG diagram like the ones output by -view-isel-dags which node type...

...I suspect that llc is assuming that HL will contain 8 (that's the start) >> and or-ing 8 with 1 or with 2 is ok. >> But my HL has also added SP to it. >> This is how my ISD::FrameIndex instruction look like: >> >> def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src), >> "ld $dst, $disp\n\tadd $dst,$src", >> [(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>; >> >> So it say that HL16:$dst wich is only HL register, will be changed. >> I also tried to change it to >> <(outs HL16:$dst), (in...

...his in the debug output: >> >> Selecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, >> Constant:i16<127> >> >> In the instruction selection phase, what pattern would that match? I've >> constructed this so far: >> >> (??? REG16:$dst, i16imm:$src) >> >> but the problem is, I can't determine what to use as ???. There is an >> ISD::CopyToReg enum value, but I don't know how that translates to the >> string to use in the pattern. >> >> And more generally, how do I find out from a DAG diagram lik...

...87 [ORD=1] [ID=1] 0x170ec00: i16 = Constant<0> [ORD=1] [ID=8] 0x170ef00: ch = BasicBlock<bb1 0x170a5d8> [ID=10] In my InstrInfo.td file I'm trying to match BRCOND as follows: let isBranch = 1 in def CondBranch : F3_1<2, 0b000101, (outs), (ins IntRegs:$L, i16imm:$R, brtarget:$dst), "; TODO: do conditional branching.", [(brcond (seteq IntRegs:$L, simm8:$R), bb:$dst)]>; I know CondBranch only handles SETEQ, but it should still match the code above (which does "icmp eq")? Or am I wrong? Thanks! / Torgny ------...

...ems: // MSA specific address operand def mem_msa : mem_generic { let MIOperandInfo = (ops ptr_rc, simm10); let EncoderMethod = "getMSAMemEncoding"; } Could you please tell me what is the simplest way to define in LD_DESC_BASE a $addrsrc that is just an immediate value like i16 or i16imm? Thank you very much, Alex

in llvm-3.6.2.src 1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file, let TwoOperandAliasConstraint = "$dst = $rs1" in { } I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction, the question is what am I doing wrong ? 2. I've noticed that TwoOperandAliasConstraint

...11, icmp ugt i32>; defm SLE : RegisterImmediateFormat<"sle", 0b011100, icmp ule i32>; defm SLT : RegisterImmediateFormat<"slt", 0b011010, icmp ult i32>; */ // memory access instructions def SWri : ImmediateFormat <0b101010, (outs), (ins DLXRegs:$a, DLXRegs:$b, i16imm:$c), !strconcat("sw", "$c($a), $b"), [/* ??? what goes here? */]>; def LWri : ImmediateFormat <0b100010, (outs DLXRegs:$dst), (ins i32imm:$b, i16imm:$c), !strconcat("lw", "$dst, $c($b)"), [/* ??? what goes her...

...ethod = "getMemOpValue"; let DecoderMethod = "DecodeMemOperand"; } def pcoffset16 : Operand<i16>, ImmLeaf<i16, [{ return Immediate >= -32768 && Immediate <= 32767; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i16imm); let ParserMatchClass = ImmediateAsmOperand<"Imm16">; let EncoderMethod = "getMemOpValue"; let DecoderMethod = "DecodeMemOperand"; } M -- Mark R V Murray

Hi, It seems like CodeEmitterGen gets confused when we use named suboperands. sample code: def memsrc : Operand<i16> { let PrintMethod = "printSrcMemOperand"; let MIOperandInfo = (ops GR16:$ra, i16imm:$imm_i16); let ParserMatchClass = memAsmOperand; } def LOAD16m : Inst32rri<0x0, (outs GR16:$rb), (ins memsrc:$src2), "ldi16 {$rb, $src2}", [(set GR16:$rb, (load addr:$src2))]>; class Inst32rri<bits<6> opcode, dag outs, dag...

...def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "add.w\t{$src2, $dst}", [(set GR16:$dst, (add GR16:$src1, GR16:$src2)), (implicit SRW)]>; } def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "add.w\t{$src2, $dst}", [(set GR16:$dst, (add GR16:$src1, imm:$src2)), (implicit SRW)]>; Regards -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/...

...m_msa : mem_generic { > let MIOperandInfo = (ops ptr_rc, simm10); > let EncoderMethod = "getMSAMemEncoding"; > } > > > > Could you please tell me what is the simplest way to define in > LD_DESC_BASE a $addrsrc > that is just an immediate value like i16 or i16imm? > > Thank you very much, > Alex > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

...in order to pick the right instructions. I couldn't find a trace of register classes in the instruction selection process. I have these patterns defined so far: def AADDMri { // Instruction MephInstr AGInstr dag OutOperandList = (outs AGRegs:$dst); dag InOperandList = (ins AGRegs:$a, i16imm:$b); list<dag> Pattern = [(set AGRegs:$dst, (add AGRegs:$a, imm:$b))]; ... } def DADDri { // Pattern Pat dag PatternToMatch = (add LSubRegs:$a, imm:$b); list<dag> ResultInstrs = [(asrsat (asextr (sextr iRSubRegs:$a), (XLoadImm imm:$b)), (i16 0))]; } where asrsat has LS...

...right instructions. I couldn't find a trace of register classes in the instruction selection process. > I have these patterns defined so far: > > def AADDMri { // Instruction MephInstr AGInstr > dag OutOperandList = (outs AGRegs:$dst); > dag InOperandList = (ins AGRegs:$a, i16imm:$b); > list<dag> Pattern = [(set AGRegs:$dst, (add AGRegs:$a, imm:$b))]; > … > } > > def DADDri { // Pattern Pat > dag PatternToMatch = (add LSubRegs:$a, imm:$b); > list<dag> ResultInstrs = [(asrsat (asextr (sextr iRSubRegs:$a), (XLoadImm imm:$b)), (i16 0))...

On Mar 7, 2012, at 6:23 AM, Ivan Llopard <ivanllopard at gmail.com> wrote: > Hi Jim, > > Thanks for your response. > > Le 06/03/2012 22:54, Jim Grosbach a écrit : >> Hi Ivan, >> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote: >> >>> Hi, >>> >>> I'm facing a problem in llvm while porting it

Hi Jim, Thanks for your response. Le 06/03/2012 22:54, Jim Grosbach a écrit : > Hi Ivan, > On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote: > >> Hi, >> >> I'm facing a problem in llvm while porting it to a new target and I'll >> need some support. >> We have 2 kind of register, one for general purposes (i.e.