Displaying 20 results from an estimated 472 matches for "r7".
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2015 Feb 10
3
[LLVMdev] Bug in ARM Thumb inline asm?
...looks like this:
...
off_t result;
return syscall(SYS__llseek, fd, offset>>32, offset, &result,
whence) ? -1 : result;
...
Which eventually goes through this macro:
static inline long __syscall5(long n, long a, long b, long c, long d,
long e)
{
register long r7 __asm__("r7") = n;
register long r0 __asm__("r0") = a;
register long r1 __asm__("r1") = b;
register long r2 __asm__("r2") = c;
register long r3 __asm__("r3") = d;
register long r4 __asm__("r4")...
2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
Hi all,
I got a silly bug when compiling our project with the latest Clang.
Here's the outputted assembly:
> tst r3, #255
> strbeq r6, [r7]
> ldreq r6, [r4, r6, lsl #2]
> strne r6, [r7, #4]
> ldr r6, [r4, r6, lsl #2]
> bx r6
For the code to execute correctly, either the _ldr_ should be a _ldrne_
instruction or the _ldreq_ instruction should be removed. The error
seems to come from the IfConvertion MachinePass. Here's...
2017 Nov 01
0
[PATCH] pmu/fuc: don't use movw directly anymore
...-- a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc
> +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc
> @@ -82,15 +82,15 @@ memx_train_tail:
> // $r0 - zero
> memx_func_enter:
> #if NVKM_PPWR_CHIPSET == GT215
> - movw $r8 0x1610
> + mov $r8 0x1610
> nv_rd32($r7, $r8)
> imm32($r6, 0xfffffffc)
> and $r7 $r6
> - movw $r6 0x2
> + mov $r6 0x2
> or $r7 $r6
> nv_wr32($r8, $r7)
> #else
> - movw $r6 0x001620
> + mov $r6 0x001620
> imm32($r7, ~0x00000aa2);
> nv...
2017 Oct 20
1
[PATCH v1 01/27] x86/crypto: Adapt assembly for PIE support
...sm_64.S
>> +++ b/arch/x86/crypto/aes-x86_64-asm_64.S
>> @@ -48,8 +48,12 @@
>> #define R10 %r10
>> #define R11 %r11
>>
>> +/* Hold global for PIE suport */
>> +#define RBASE %r12
>> +
>> #define prologue(FUNC,KEY,B128,B192,r1,r2,r5,r6,r7,r8,r9,r10,r11) \
>> ENTRY(FUNC); \
>> + pushq RBASE; \
>> movq r1,r2; \
>> leaq KEY+48(r8),r9; \
>> movq r10,r11; \
>> @@ -74,54 +78,63 @@
>>...
2017 Oct 20
1
[PATCH v1 01/27] x86/crypto: Adapt assembly for PIE support
...sm_64.S
>> +++ b/arch/x86/crypto/aes-x86_64-asm_64.S
>> @@ -48,8 +48,12 @@
>> #define R10 %r10
>> #define R11 %r11
>>
>> +/* Hold global for PIE suport */
>> +#define RBASE %r12
>> +
>> #define prologue(FUNC,KEY,B128,B192,r1,r2,r5,r6,r7,r8,r9,r10,r11) \
>> ENTRY(FUNC); \
>> + pushq RBASE; \
>> movq r1,r2; \
>> leaq KEY+48(r8),r9; \
>> movq r10,r11; \
>> @@ -74,54 +78,63 @@
>>...
2007 Dec 02
2
Optimised qmf_synth and iir_mem16
...@ Clip negative
strh r14, [r2], #2 @ Write result to y[i]
ldrsh r4, [r1]
ldrsh r0, [r1, #2]
rsb r14,r14,#0 @ r14 = -y[i]
mla r5, r4, r14,r6 @ mem[0] = mem[1] - den[0]*y[i]
ldrsh r4, [r1, #4]
mla r6, r0, r14,r7 @ mem[1] = mem[2] - den[1]*y[i]
ldrsh r0, [r1, #6]
mla r7, r4, r14,r8 @ mem[2] = mem[3] - den[2]*y[i]
ldrsh r4, [r1, #8]
mla r8, r0, r14,r9 @ mem[3] = mem[4] - den[3]*y[i]
ldrsh r0, [r1, #10]
mla r9, r4, r14,r10 @ mem[4] =...
2017 Nov 01
2
[PATCH] pmu/fuc: don't use movw directly anymore
.../subdev/pmu/fuc/memx.fuc
index ec03f9a4..1663bf94 100644
--- a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc
+++ b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc
@@ -82,15 +82,15 @@ memx_train_tail:
// $r0 - zero
memx_func_enter:
#if NVKM_PPWR_CHIPSET == GT215
- movw $r8 0x1610
+ mov $r8 0x1610
nv_rd32($r7, $r8)
imm32($r6, 0xfffffffc)
and $r7 $r6
- movw $r6 0x2
+ mov $r6 0x2
or $r7 $r6
nv_wr32($r8, $r7)
#else
- movw $r6 0x001620
+ mov $r6 0x001620
imm32($r7, ~0x00000aa2);
nv_rd32($r8, $r6)
and $r8 $r7
@@ -101,7 +101,7 @@ memx_func_enter:
and $r8 $r7
nv_wr32($r6, $r8)
- movw $r6 0...
2005 Jul 20
1
MMX IDCT for theora-exp
...ne Dump "call MMX_dump\n"
+
+#define BeginIDCT "#BeginIDCT\n"\
+ \
+ " movq " I(3)","r2"\n" \
+ \
+ " movq " C(3)","r6"\n" \
+ " movq " r2","r4"\n" \
+ " movq " J(5)","r7"\n" \
+ " pmulhw " r6","r4"\n" \
+ " movq " C(5)","r1"\n" \
+ " pmulhw " r7","r6"\n" \
+ " movq " r1","r5"\n" \
+ " pmulhw " r2","r1"\n"...
2016 Jan 04
1
Nouveau support for GeForce GT 730 or GTX 750 Ti or AMD Radeon R7 240 and AMD ATI RADEON R7 260X ??
2016-01-03 20:11 GMT+01:00 Ilia Mirkin <imirkin at alum.mit.edu>:
> On Sun, Jan 3, 2016 at 1:52 PM, Csányi Pál <csanyipal at gmail.com> wrote:
>> So there is an AMD card too:
>> VGA ASUS AMD Radeon R7 240, R7240-2GD3-L, 2GB DDR3, 128bit,
>> 730/1800MHz, HDMI, DVI-D, D-sub
>>
>> What would be the best choice here:
>> GEFORCE GT 730
>> or
>> AMD Radeon R7 240 ?
>
> I don't want to recommend one or the other, esp as I'm unaware of the
> specifics...
2017 Oct 20
0
[PATCH v1 01/27] x86/crypto: Adapt assembly for PIE support
...644
> --- a/arch/x86/crypto/aes-x86_64-asm_64.S
> +++ b/arch/x86/crypto/aes-x86_64-asm_64.S
> @@ -48,8 +48,12 @@
> #define R10 %r10
> #define R11 %r11
>
> +/* Hold global for PIE suport */
> +#define RBASE %r12
> +
> #define prologue(FUNC,KEY,B128,B192,r1,r2,r5,r6,r7,r8,r9,r10,r11) \
> ENTRY(FUNC); \
> + pushq RBASE; \
> movq r1,r2; \
> leaq KEY+48(r8),r9; \
> movq r10,r11; \
> @@ -74,54 +78,63 @@
> movl r6 ## E,4(r9); \
> movl r7 ## E,8(r9); \
> movl r8 ## E,12(r9); \
> + popq RBASE; \
> ret; \
&...
2019 Aug 21
3
Thumb frame pointer register
Hello all,
I noticed that for ARM Thumb target, llc uses r7 as frame pointer (gcc does
not do this AFAIK), and this register should therefore not be used as a
general-purpose register.
However, when compiling mbedTLS, which contains some code that is highly
optimized for ARM platform and uses r7 to efficiently perform an operation.
This raises an exception...
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
Hi Craig,
Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7?
I tried to search in ARMInstrThumb.td but couldn’t find it.
Thanks,
- Jie
On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote:
I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2...
2006 May 28
2
Lotus Notes R7 on Wine
Hello
I currently trying to run the Domino Client (Lotus Notes R7) on Wine 0.9.14 but couldn't get success yet.
Does somebody has experience about running the R7 on Wine? I tried a lot of diffrent WINEDLLOVERRIDES settings but all I get is that Lotus brings the crash dialog (which creates a crash error message). I would be very appreciative for any hint.
Ro...
2019 Apr 14
3
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
Hi all,
I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird.
For an add, when I use
BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm).
if reg is R0 - R7, everything is fine: I would get something like
adds r1, 4
But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register in the assembly code. For example, when I pass R8 to it, I would get
adds r0, 4
rather than
adds r8, 4.
Similar problems happen to push and pop i...
2017 Dec 01
2
Some strange i64 behavior with arm 32bit. (Raspberry Pi)
Hi Tim,
thanks for the swift response!
@debug is defined in the same module, which makes this all the more confusing.
The target information from the working example are:
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv6kz--linux-gnueabihf"
from the ghc produced module:
target datalayout =
2006 Jun 26
0
[klibc 22/43] arm support for klibc
...0..1841bc7
--- /dev/null
+++ b/usr/klibc/arch/arm/setjmp.S
@@ -0,0 +1,102 @@
+#
+# arch/arm/setjmp.S
+#
+# setjmp/longjmp for the ARM architecture
+#
+
+#ifndef __thumb__
+
+#
+# "Pure ARM" version
+#
+# The jmp_buf is assumed to contain the following, in order:
+# r4
+# r5
+# r6
+# r7
+# r8
+# r9
+# r10
+# fp
+# sp
+# lr
+#
+
+ .text
+ .balign 4
+ .globl setjmp
+ .type setjmp, #function
+setjmp:
+ stmia r0, {r4, r5, r6, r7, r8, r9, r10, fp, sp, lr}
+ mov r0, #0
+ mov pc, lr
+ .size setjmp,.-setjmp
+
+ .text
+ .balign 4
+ .globl longjmp
+ .type longjmp, #function
+longjmp:...
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
...g from an inline asm. After the “Post RA top-down list
latency scheduler” pass, the cmp instruction has been moved before the
inline asm causing the issue.
198: e35c0001 cmp ip, #1 <<<<<<<<<<<<<<<<<<
19c: e023700e eor r7, r3, lr
1a0: e0022003 and r2, r2, r3
1a4: e0087007 and r7, r8, r7
1a8: e1820007 orr r0, r2, r7
1ac: e1b42e9f ldaexd r2, r3, [r4]
1b0: e1a46f90 strexd r6, r0, [r4]
1b4: e3560000 cmp r6, #0
1b8: 1afffffb bne 1ac <...
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
...nerate mov instructions but
not add/sub and push/pop confuses me.
- Jie
On Apr 14, 2019, at 14:55, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote:
I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7.
tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument.
~Craig
On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <llvm-dev at lists.l...
2011 May 26
2
[LLVMdev] LLVM CodeGen Engineer job opening with Apple's compiler team
Hi all,
LLVM CodeGen and Tools team at Apple is looking for exceptional compiler engineers. This is a great opportunity to work with many of the leaders in the LLVM community.
If you are interested in this position, please send your resume / CV and relevant information to evan.cheng at apple.com
Thanks,
Evan
Job description
The Apple compiler team is seeking an engineer who is strongly
2011 May 27
1
[LLVMdev] Question about ARM/vfp/NEON code generation
...re?
thanks,
-David
.private_extern _FloatingPointTest
.globl _FloatingPointTest
.align 2
_FloatingPointTest: @ @FloatingPointTest
@ BB#0: @ %entry
sub sp, sp, #8
str lr, [sp, #4]
str r7, [sp]
mov r7, sp
sub sp, sp, #36
str r0, [r7, #-4]
vmov s0, r0
str r1, [r7, #-8]
vmov s1, r1
str r2, [r7, #-12]
vmov s2, r2
vldr.32 s3, [r7, #-4]
vldr.32 s4, [r7, #-8]
vmul.f32...