search for: cr7

...re %>% group_by(StorePC, StoreX, StoreY) %>% summarize(meanPrice=(mean(RetailPrice))) which results in . > priceStore_Grps # A tibble: 15 x 4 # Groups: StorePC, StoreX [?] StorePC StoreX StoreY meanPrice <fct> <int> <int> <dbl> 1 CR7 8LE 532714 168302 472. 2 E2 0RY 535652 182961 520. 3 E7 8NW 541428 184515 467. 4 KT2 5AU 517917 170243 522. 5 N17 6QA 533788 189994 523. Which is fine, but I then want to give each group (e.g. CR7 8LE 532714 168302) a unique identifier (say) Store 1, 2, 3 or...

...e))) > > > > which results in . > > > >> priceStore_Grps > > # A tibble: 15 x 4 > > # Groups: StorePC, StoreX [?] > > StorePC StoreX StoreY meanPrice > > <fct> <int> <int> <dbl> > > 1 CR7 8LE 532714 168302 472. > > 2 E2 0RY 535652 182961 520. > > 3 E7 8NW 541428 184515 467. > > 4 KT2 5AU 517917 170243 522. > > 5 N17 6QA 533788 189994 523. > > > > Which is fine, but I then want to give each group (e.g. CR7 8...

...esults in . >> >> >>> priceStore_Grps >> >> # A tibble: 15 x 4 >> >> # Groups:?? StorePC, StoreX [?] >> >> ??? StorePC? StoreX StoreY meanPrice >> >> ??? <fct>???? <int>? <int>???? <dbl> >> >> 1 CR7 8LE? 532714 168302????? 472. >> >> 2 E2 0RY?? 535652 182961????? 520. >> >> 3 E7 8NW?? 541428 184515????? 467. >> >> 4 KT2 5AU? 517917 170243????? 522. >> >> 5 N17 6QA? 533788 189994????? 523. >> >> >> Which is fine, but I then want...

...the non-callee saved registers... Defs = [{ static const unsigned Defs_ELF[] = {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10, V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, LR,CTR, CR0,CR1,CR5,CR6,CR7} static const unsigned Defs_Macho[] = {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, LR,CTR, CR0,CR1,CR5,CR6,CR7} GPRClass::iterator...

Is there any reason why we can't generate HWEncoding based decoders for registers for mc disassemblers? This is a concept patch to explore wether it'd work, and for my target, it does the right thing. I have one case where I have to shift a field over 2 bits, but I handle that in the glue. If I had a HWEncoding encoding on a per register class basis, I could have made it work without

...> Defs = [{ > > > static const unsigned Defs_ELF[] = > {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, > F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10, > > V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, > LR,CTR, > CR0,CR1,CR5,CR6,CR7} > > static const unsigned Defs_Macho[] = > {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, > F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, > > V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, > LR,CTR, > CR0,CR1,CR5,CR6,CR7} &...

On Fri, 2 Feb 2007, Nicolas Geoffray wrote: > I have almost completed the implementation of a linux/ppc backend in llvm. Cool! > There were a few things to modify in > lib/Target/PowerPC with a lot of "if (!isDarwin)". Some meta comments: 1. Please don't change PPC -> llvmPPC. I assume that you did this because PPC is a #define in some system header. Please

...rom lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp: > > // FIXME: These can be generated by TableGen from the existing register > // encoding values! > > static const unsigned CRRegs[] = { > PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, > PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 > }; Yeah, my code does this for free: extern const uint16_t PPCRegDecodingTable_CRRC[] = { /* [0] = */ PPC::CR0, /* [1] = */ PPC::CR1, /* [2] = */ PPC::CR2, /* [3] = */ PPC::CR3, /* [4] = */ PPC::CR4, /* [5] = */ PPC::CR5, /* [6] = */ PPC::CR6, /* [7] = */ PPC::CR7, }; > s...

Hi everyone, I have almost completed the implementation of a linux/ppc backend in llvm. There were a few things to modify in lib/Target/PowerPC with a lot of "if (!isDarwin)". There are some places where I need help before saying the port is complete. I attached the diff file as a reference 1) In order to generate a creqv instruction before a vararg call, I created a new

On Mon, 11 Jun 2012 08:56:21 -0700 Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 11, 2012, at 8:07 AM, Hal Finkel wrote: > > > Also, I think the following might work well: If we add a special > > kind of register dependency called a 'remembered' register. This is > > not a real dependency meaning that that the instruction does not >

On Thu, 17 Jan 2013 22:22:47 -0500 Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> wrote: > Jan had some comments about that patch: > > https://patchwork.kernel.org/patch/1745041/ > > Please fix it up so I can put it in the Linux tree. Please see below. Signed-off-by: Mukesh Rathor <mukesh.rathor@oracle.com> Thanks, Mukesh diff --git a/arch/x86/xen/xen-head.S

.../* PVH: GDTR addr and size */ + unsigned long gdtaddr, gdtsz; + } pvh; + } u; unsigned long kernel_ss, kernel_sp; /* Virtual TSS (only SS1/SP1) */ /* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */ unsigned long ctrlreg[8]; /* CR0-CR7 (control registers) */ diff --git a/sys/xen/pv.h b/sys/xen/pv.h new file mode 100644 index 0000000..bbb1048 --- /dev/null +++ b/sys/xen/pv.h @@ -0,0 +1,29 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files...

This patch series implements the Linux Xen guest in terms of the paravirt-ops interface. The features in implemented this patch series are: * domU only * UP only (most code is SMP-safe, but there's no way to create a new vcpu) * writable pagetables, with late pinning/early unpinning (no shadow pagetable support) * supports both PAE and non-PAE modes * xen console * virtual block

This patch series implements the Linux Xen guest in terms of the paravirt-ops interface. The features in implemented this patch series are: * domU only * UP only (most code is SMP-safe, but there's no way to create a new vcpu) * writable pagetables, with late pinning/early unpinning (no shadow pagetable support) * supports both PAE and non-PAE modes * xen console * virtual block

This patch series implements the Linux Xen guest in terms of the paravirt-ops interface. The features in implemented this patch series are: * domU only * UP only (most code is SMP-safe, but there's no way to create a new vcpu) * writable pagetables, with late pinning/early unpinning (no shadow pagetable support) * supports both PAE and non-PAE modes * xen console * virtual block

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hi Andi, This patch series implements the Linux Xen guest as a paravirt_ops backend. The features in implemented this patch series are: * domU only * UP only (most code is SMP-safe, but there's no way to create a new vcpu) * writable pagetables, with late pinning/early unpinning (no shadow pagetable support) * supports both PAE and non-PAE modes * xen hvc console (console=hvc0) *

Hi Andi, This patch series implements the Linux Xen guest as a paravirt_ops backend. The features in implemented this patch series are: * domU only * UP only (most code is SMP-safe, but there's no way to create a new vcpu) * writable pagetables, with late pinning/early unpinning (no shadow pagetable support) * supports both PAE and non-PAE modes * xen hvc console (console=hvc0) *

Hi Andi, This patch series implements the Linux Xen guest as a paravirt_ops backend. The features in implemented this patch series are: * domU only * UP only (most code is SMP-safe, but there's no way to create a new vcpu) * writable pagetables, with late pinning/early unpinning (no shadow pagetable support) * supports both PAE and non-PAE modes * xen hvc console (console=hvc0) *