Displaying 20 results from an estimated 96 matches for "patfrags".
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patfrag
2020 Jul 13
2
[Beginner] Understanding Tablegen language
...2. Entity followed after "(" is always need to be an operator? or it can be
ValueType or something else?
3. What are keywords like "ins", "outs" and "ops"? They are not mentioned
in lang ref manual either.
4. What is a "node" keyword?
5. How are PatFrags used? I see some .td files I see, like X86InstrFMA.td,
PatFrag MemFrag is passed as argument to multiclass and then used along
with addr:$src3 in it. I really don't understand what this means. Does this
mean that whatever comes after PatFrag "object" is substituted as Args in
PatFrag?...
2012 May 11
2
[LLVMdev] TableGen pattern for negated operand
I've been unable to come up with the TableGen recipe to match a
negated operand. My target asm syntax allows the following transform:
FNEG r8, r5
MUL r6, r8, r9
to
MUL r6, -r5, r9
Is there a Pattern<> syntax that would allow matching *any* opcode (or
even some subset), not just MUL, with a FNEG'd operand? I expect I can
define a PatFrag:
def fneg_su : PatFrag<(ops
2012 Jun 20
2
[LLVMdev] How to define macros in a tablegen file?
On Wed, Jun 20, 2012 at 12:26 PM, Sebastian Pop <spop at codeaurora.org> wrote:
> For reference, here is how the SPU port is using code and pattern fragments:
>
> // Holder of code fragments (you'd think this'd already be in
> // a td file somewhere... :-)
And this comment makes me think, shouldn't this class CodeFrag be
included in the same place where PatFrag is
2012 May 11
0
[LLVMdev] TableGen pattern for negated operand
Hi Joe,
Le 11/05/2012 02:13, Joe Matarazzo a écrit :
> I've been unable to come up with the TableGen recipe to match a
> negated operand. My target asm syntax allows the following transform:
>
> FNEG r8, r5
> MUL r6, r8, r9
>
> to
>
> MUL r6, -r5, r9
>
> Is there a Pattern<> syntax that would allow matching *any* opcode (or
> even some
2014 Jun 11
2
[LLVMdev] Help regarding ad new functionality in Backend
Dear,
I am looking at the Instructions defined in the XXXXInstrInfo.td where I
can see a def record defined like below
def ADD8rr : I8rr<0x0,
(outs GR8:$dst), (ins GR8:$src, GR8:$src2),
"add.b\t{$src2, $dst}",
[(set GR8:$dst, (*add *GR8:$src, GR8:$src2)),
(implicit SRW)]>;
Now here I would like the to
2011 Aug 24
1
[LLVMdev] proposal: add macro expansion of for-loop to TableGen
Hi folks,
TableGen provides sufficiently rich syntax for expressing target
instruction set. Nevertheless, when I wrote the PTX backend, I
observed that some redundancy in TableGen can be further eliminated
through macro expansion of for-loops.
The semantics of a for-loop is expanding the for-loop body, and so it
is equivalent to manually unroll the loop (see example #1).
I believe the for-loop
2011 Sep 13
3
[LLVMdev] Setting priority in instruction selection
I am having a problem with instruction selection with pattern fragments.
With my custom target, in order to simplify code generation patterns, I do not allow a constant to be used in an instruction(mainly because they have declare before use semantics).
Now the problem I am having is that I cannot get a instruction that contains pattern fragment that uses an immediate value to be selected before
2011 May 09
0
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
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陳韋任 wrote:
<blockquote cite="mid:20110509013918.GA13760@cs.nctu.edu.tw" type="cite">
2011 May 09
3
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
Hi, Justin
> We're been writing multiclasses for each unique type of instruction. The
> current PTX_LOGIC version is for 3-operand instructions. A new multiclass
> needs to be created for 2-operand logic instructions.
I am trying to add a multiclass for 2-operand logic instructions. For
example,
multiclass PTX_LOGIC_2OP<string opcstr, SDNode opnode> {
def ripreds :
2012 Jun 20
0
[LLVMdev] How to define macros in a tablegen file?
For reference, here is how the SPU port is using code and pattern fragments:
// Holder of code fragments (you'd think this'd already be in
// a td file somewhere... :-)
class CodeFrag<dag frag> {
dag Fragment = frag;
}
class I64SETCCNegCond<PatFrag cond, CodeFrag compare>:
Pat<(cond R64C:$rA, R64C:$rB),
(XORIr32 compare.Fragment, -1)>;
def :
2012 Jun 20
0
[LLVMdev] How to define macros in a tablegen file?
On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at codeaurora.org> wrote:
> On Wed, Jun 20, 2012 at 12:26 PM, Sebastian Pop <spop at codeaurora.org> wrote:
>> For reference, here is how the SPU port is using code and pattern fragments:
>>
>> // Holder of code fragments (you'd think this'd already be in
>> // a td file somewhere... :-)
>
>
2012 Jun 20
3
[LLVMdev] How to define macros in a tablegen file?
Hi Micah,
On Tue, Jun 19, 2012 at 6:29 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> If the patterns only include SDNodes, then pattern fragments will work.
>
> I might be wrong, but I've yet to find a way to do it with machine instructions, which is what you seem to have here.
I found in the Cell SPU port: lib/Target/CellSPU/SPUMathInstr.td
some examples using code
2012 Jun 20
3
[LLVMdev] How to define macros in a tablegen file?
Possible to add a test case?
Micah
> -----Original Message-----
> From: Sebastian Pop [mailto:spop at codeaurora.org]
> Sent: Wednesday, June 20, 2012 1:40 PM
> To: Villmow, Micah
> Cc: llvmdev at cs.uiuc.edu; llvm-commits at cs.uiuc.edu
> Subject: Re: [LLVMdev] How to define macros in a tablegen file?
>
> On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at
2016 Dec 09
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...pefully this will get you closer to what you need:
If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition.
It allows a PatFrag be passed into the avx512_gather multiclass definition.
Working backwards from here, the actual PatFrags passed into this are things like ‘mgatherv4i32’. These are patterns that match a MaskedGatherSDNode for a particular data type.
MaskedGatherSDNode is the generic SD node that represents a predicated gather, which in turn was generated from Intrinsic::masked_gather in the IR (in SelectionDAGBuilde...
2011 Sep 13
0
[LLVMdev] Setting priority in instruction selection
On Mon, Sep 12, 2011 at 6:53 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> I am having a problem with instruction selection with pattern fragments.
>
> With my custom target, in order to simplify code generation patterns, I do
> not allow a constant to be used in an instruction(mainly because they have
> declare before use semantics).
>
>
>
> Now the
2008 Oct 06
1
[LLVMdev] sign extensions on loads?
I have a simple test case that my code generator handles fine when using
optimizations, but when I disable optimizations, It turns into a
sequence of instructions that I can't figure out what to setup to get it
to generate the correct code.
The instructions in question are:
%tmp1 = load float* %test ; <float> [#uses=1]
%conv = fpext float %tmp1 to double ;
2011 Sep 13
1
[LLVMdev] Setting priority in instruction selection
> -----Original Message-----
> From: Eli Friedman [mailto:eli.friedman at gmail.com]
> Sent: Monday, September 12, 2011 7:15 PM
> To: Villmow, Micah
> Cc: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Setting priority in instruction selection
>
> On Mon, Sep 12, 2011 at 6:53 PM, Villmow, Micah <Micah.Villmow at amd.com>
> wrote:
> > I am having a problem
2019 Sep 10
2
tablegen exponential behavior
Hi,
I implemented a pattern matching of the dot product for arm64
and it seemed to work well for the basic case, i.e.,
class mulB<SDPatternOperator ldop> :
PatFrag<(ops node:$Rn, node:$Rm, node:$offset),
(mul (ldop (add node:$Rn, node:$offset)),
(ldop (add node:$Rm, node:$offset)))>;
class mulBz<SDPatternOperator ldop> :
PatFrag<(ops node:$Rn,
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...oser to what you need:
>
> If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’
> is a template argument, not a definition.
> It allows a PatFrag be passed into the avx512_gather multiclass definition.
>
> Working backwards from here, the actual PatFrags passed into this are things like
> ‘mgatherv4i32’. These are patterns that match a MaskedGatherSDNode for a particular data
> type.
>
> MaskedGatherSDNode is the generic SD node that represents a predicated gather, which in
> turn was generated from Intrinsic::masked_gather in the I...
2010 Aug 04
2
[LLVMdev] x86 Vector Shuffle Patterns
I have a few questions about the new vector shuffle matching code in the
x86 .td files. It's a big improvement over the old system and provides
the context that code generation for AVX needs. This is great!
I'm asking because I'm having some trouble converting some AVX patterns
over to the new system. I'm getting this error from tblgen:
VyPERM2F128PDirrmi: (set:isVoid