search for: oldval

...d to both C and X86 in this matter. A weak cmpxchg would go a long way to resolving this, but it's still difficult to see a path from an IR-level "cmpxchg weak" to optimal "atomicrmw lambda" support in LL/SC backends. Given C like void atomic_foo(int *addr) { int oldval = *addr; do { newval = foo(oldval); } while (__c11_compare_exchange_weak(addr, &oldval, newval)); The cmpxchg representation would be something like: define void @atomic_foo(int *addr) { entry: %firstval = load i32* %addr br label %loop loop:...

Quoting Tim Northover <t.p.northover at gmail.com>: > On 24 April 2015 at 13:53, Tyler Denniston <tyler at csail.mit.edu> wrote: >> I'm wondering how I can create an atomic load and add instruction for >> floating point values. If I use IRBuilder::CreateAtomicRMW() I get the >> error message: "atomicrmw operand must have integer type". > >

...ntrol flow earlier. For example the return value of the C++11 and C11 compare_exchange operations is actually whether the exchange succeeded, which leads to some common idioms in Clang-produced IR. >From "if(__c11_compare_exchange_strong(...))": %loaded = cmpxchg i32* %addr, i32 %oldval, i32 %newval seq_cst seq_cst %success = icmp eq i32 %loaded, %oldval br i1 %success, label %true, label %false the control-flow here should be something like: loop: %loaded = load linked i32* %addr seq_cst %trystore = icmp eq %loaded, %oldval br i1 %trystore, label %st...

> } while (__c11_atomic_compare_exchange_weak( > addr, &oldval, newval, memory_order_seq_cst, memory_order_relaxed)); Actually, I think this condition is inverted. Should be "while (!_c11...". Sorry about that. Tim.

I have backgroundrb working locally and everything''s fine. However, i can''t get it running on our server. I read a blog post by David Burger about backgroundrb (http://david-burger.blogspot.com/2008/04/backgroundrb-rails-notes.html#comment-form) and it says that you set up your backgroundrb.yml file with a different section for each environment you want to use. Mine looks like

...rites: > >> Ah, I think I get it now. This was mentioned earlier in the thread, >> but it didn't click at the time. It sounds like I can do instruction >> selection with a pattern like (omitting selection of the sources): >> >> let Constraints = "$dst = $oldvalue" in { >> def MASKEDARITH : MyInstruction< >> (outs VectorReg:$dst), >> (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2, >> VectorReg:$oldvalue), >> "add $dst {$mask}, $src1, $src2", >> [(set v16i32:$dst, (vs...

Does anyone know what application I should place this function in? For example with the DB function I currently do something like this to add an entry to the asterisk database: exten => s,n,Set(DB(AGENT/${MACRO_EXTEN:1})=${CALLERID(num)}) To delete the entries I do something like this: exten => s,n,DBDel(AGENT/${MACRO_EXTEN:1}) DBDel is marked as deprecated in favor of the DB_DELETE

..._mods > 0) { + char thishost[NI_MAXHOST]; + + if (gethostname(thishost, sizeof(thishost)) == -1) + fatal("gethostname: %s", strerror(errno)); + snprintf(buf, sizeof(buf), "%d", options.port); + + for (i = 0; i < options.num_local_env_mods; i++) { + char sepbuf[2], *oldval; + int prepend = 0; + int op = options.local_env_mods[i].operation; + if (0 > op) { + prepend = 1; + op = -op; + } + sepbuf[0] = op; + sepbuf[1] = '\0'; + debug3("expanding LocalEnvMod: %s %s%s= %s", + options.local_env_mods[i].name, + op ? (prep...

...i Chris, I'd prefer to fix the lowering if possible; the pseudo instructions are only used in three places, so it shouldn't be a huge change. I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP however: how do I do that? FWIW the code it needs to emit is: ; inputs: ptr, oldval, newval loop: lwarx $tmp, 0, $ptr cmpw $oldval, $tmp bne- exit stwcx. $newval, 0, $ptr bne- loop exit: ... Cheers, Gary -- http://gbenson.net/

...bush001 at gmail.com> writes: > Ah, I think I get it now. This was mentioned earlier in the thread, > but it didn't click at the time. It sounds like I can do instruction > selection with a pattern like (omitting selection of the sources): > > let Constraints = "$dst = $oldvalue" in { > def MASKEDARITH : MyInstruction< > (outs VectorReg:$dst), > (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2, > VectorReg:$oldvalue), > "add $dst {$mask}, $src1, $src2", > [(set v16i32:$dst, (vselect v16i1:$mask,...

...struct nvkm_device *device = subdev->device; + u32 addr = nvbios_rd32(bios, init->offset + 1); + u8 incr = nvbios_rd08(bios, init->offset + 5); + u8 num = nvbios_rd08(bios, init->offset + 6); + u8 count = nvbios_ramcfg_count(init->bios); + u8 index = init->ramcfg; + u8 i; + u32 oldval, newval; + + init->offset += 7; + + for (i = 0; i < num; i++) { + oldval = nvkm_rd32(device, addr); + newval = nvbios_rd32(bios, init->offset + (4 * index)); + + if (oldval != newval) { + nvkm_memx_wr32(memx, addr, newval); + } + init->offset += 4 * count; + addr += incr; + } +...

...;__gconv_release_step") at assert.c:50 50 { (gdb) 54 FATAL_PREPARE; (gdb) __pthread_setcancelstate (state=1, oldstate=0x0) at pthread_setcancelstate.c:29 29 { (gdb) 32 if (state < PTHREAD_CANCEL_ENABLE || state > PTHREAD_CANCEL_DISABLE) (gdb) 37 int oldval = THREAD_GETMEM (self, cancelhandling); (gdb) 42 : oldval & ~CANCELSTATE_BITMASK); (gdb) 45 if (oldstate != NULL) (gdb) 52 if (oldval == newval) (gdb) 57 int curval = THREAD_ATOMIC_CMPXCHG_VAL (self, cancelhandling, newval, (gdb) 59...

...r to fix the lowering if possible; the pseudo instructions > are only used in three places, so it shouldn't be a huge change. > I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP > however: how do I do that? FWIW the code it needs to emit is: > > ; inputs: ptr, oldval, newval > loop: > lwarx $tmp, 0, $ptr > cmpw $oldval, $tmp > bne- exit > stwcx. $newval, 0, $ptr > bne- loop > exit: > ... > > > Cheers, > Gary > > -- > http://gbenson.net/ > _______________________________...

On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > $label), > "cmpw $rA, $rB\n\tbne- La${label}_exit", > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > $label)]>; > } > > ...and I can't figure out the syntax for that. Any suggestions? Hi

...turn DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3); } SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2762,39 +2743,14 @@ SDOperand NewVal = Op.getOperand(2); SDOperand OldVal = Op.getOperand(3); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { -...

Hi all, I'm trying to figure out how to add the instructions required for llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne-

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...tOps[] = { Load, Store }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3); } SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2762,39 +2743,14 @@ SDOperand NewVal = Op.getOperand(2); SDOperand OldVal = Op.getOperand(3); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { -...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const