I believe I've addressed all the feedback from the first time around, and also made fixes necessary for GM20x based on testing results. I believe now it should actually work for all GM10x and GM20x. Further, GP10x should be very easy to add, but without someone to actually test I didn't want to claim support for it. Ilia Mirkin (7): exa: add GM10x acceleration support hwdefs: update nvc0_3d, add gm107_texture for new TIC format nvc0: make use of the new hwdefs for TEX_CB_INDEX nvc0: rename BEGIN_IMC0 to IMMED_NVC0 nvc0: refactor TIC uploads to allow different specifics per generation copy: add maxwell/pascal copy engine classes recognize and accelerate GM20x src/Makefile.am | 17 + src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++ src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++---------------- src/nouveau_copy.c | 3 + src/nouveau_exa.c | 2 +- src/nouveau_local.h | 2 +- src/nouveau_xv.c | 2 +- src/nv_accel_common.c | 1 + src/nv_driver.c | 3 + src/nvc0_accel.c | 68 +++- src/nvc0_accel.h | 57 +++ src/nvc0_exa.c | 71 ++-- src/nvc0_xv.c | 115 +++--- src/shader/Makefile | 23 +- src/shader/exac8nv110.fp | 47 +++ src/shader/exac8nv110.fpc | 38 ++ src/shader/exacanv110.fp | 47 +++ src/shader/exacanv110.fpc | 38 ++ src/shader/exacmnv110.fp | 47 +++ src/shader/exacmnv110.fpc | 38 ++ src/shader/exas8nv110.fp | 42 ++ src/shader/exas8nv110.fpc | 28 ++ src/shader/exasanv110.fp | 47 +++ src/shader/exasanv110.fpc | 38 ++ src/shader/exascnv110.fp | 38 ++ src/shader/exascnv110.fpc | 20 + src/shader/videonv110.fp | 54 +++ src/shader/videonv110.fpc | 52 +++ src/shader/xfrm2nv110.vp | 82 ++++ src/shader/xfrm2nv110.vpc | 102 +++++ 30 files changed, 1928 insertions(+), 426 deletions(-) create mode 100644 src/hwdefs/gm107_texture.xml.h create mode 100644 src/shader/exac8nv110.fp create mode 100644 src/shader/exac8nv110.fpc create mode 100644 src/shader/exacanv110.fp create mode 100644 src/shader/exacanv110.fpc create mode 100644 src/shader/exacmnv110.fp create mode 100644 src/shader/exacmnv110.fpc create mode 100644 src/shader/exas8nv110.fp create mode 100644 src/shader/exas8nv110.fpc create mode 100644 src/shader/exasanv110.fp create mode 100644 src/shader/exasanv110.fpc create mode 100644 src/shader/exascnv110.fp create mode 100644 src/shader/exascnv110.fpc create mode 100644 src/shader/videonv110.fp create mode 100644 src/shader/videonv110.fpc create mode 100644 src/shader/xfrm2nv110.vp create mode 100644 src/shader/xfrm2nv110.vpc -- 2.7.3
Ilia Mirkin
2016-Oct-27 14:02 UTC
[Nouveau] [PATCH v2 1/7] exa: add GM10x acceleration support
rendercheck -f a8r8g8b8 passes as much as on a GK208, and xv appears to
work. Very lightly tested.
Instead of sticking coordinates into pushbufs, the vertex shader is
modified to read them from a constbuf, indexed by vertex id. This
approach could be used for all nvc0 generations, but I didn't want to
rock the boat.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/Makefile.am | 16 ++++++++
src/nouveau_copy.c | 1 +
src/nouveau_exa.c | 2 +-
src/nouveau_xv.c | 2 +-
src/nv_accel_common.c | 1 +
src/nv_driver.c | 1 +
src/nvc0_accel.c | 37 ++++++++++++++---
src/nvc0_exa.c | 48 ++++++++++++++++++++--
src/nvc0_xv.c | 48 ++++++++++++++++++++--
src/shader/Makefile | 23 ++++++++---
src/shader/exac8nv110.fp | 47 +++++++++++++++++++++
src/shader/exac8nv110.fpc | 38 +++++++++++++++++
src/shader/exacanv110.fp | 47 +++++++++++++++++++++
src/shader/exacanv110.fpc | 38 +++++++++++++++++
src/shader/exacmnv110.fp | 47 +++++++++++++++++++++
src/shader/exacmnv110.fpc | 38 +++++++++++++++++
src/shader/exas8nv110.fp | 42 +++++++++++++++++++
src/shader/exas8nv110.fpc | 28 +++++++++++++
src/shader/exasanv110.fp | 47 +++++++++++++++++++++
src/shader/exasanv110.fpc | 38 +++++++++++++++++
src/shader/exascnv110.fp | 38 +++++++++++++++++
src/shader/exascnv110.fpc | 20 +++++++++
src/shader/videonv110.fp | 54 ++++++++++++++++++++++++
src/shader/videonv110.fpc | 52 +++++++++++++++++++++++
src/shader/xfrm2nv110.vp | 82 +++++++++++++++++++++++++++++++++++++
src/shader/xfrm2nv110.vpc | 102 ++++++++++++++++++++++++++++++++++++++++++++++
26 files changed, 918 insertions(+), 19 deletions(-)
create mode 100644 src/shader/exac8nv110.fp
create mode 100644 src/shader/exac8nv110.fpc
create mode 100644 src/shader/exacanv110.fp
create mode 100644 src/shader/exacanv110.fpc
create mode 100644 src/shader/exacmnv110.fp
create mode 100644 src/shader/exacmnv110.fpc
create mode 100644 src/shader/exas8nv110.fp
create mode 100644 src/shader/exas8nv110.fpc
create mode 100644 src/shader/exasanv110.fp
create mode 100644 src/shader/exasanv110.fpc
create mode 100644 src/shader/exascnv110.fp
create mode 100644 src/shader/exascnv110.fpc
create mode 100644 src/shader/videonv110.fp
create mode 100644 src/shader/videonv110.fpc
create mode 100644 src/shader/xfrm2nv110.vp
create mode 100644 src/shader/xfrm2nv110.vpc
diff --git a/src/Makefile.am b/src/Makefile.am
index 1e04ddf..6ba8d87 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -77,48 +77,64 @@ EXTRA_DIST = hwdefs/nv_3ddefs.xml.h \
shader/exac8nve0.fpc \
shader/exac8nvf0.fp \
shader/exac8nvf0.fpc \
+ shader/exac8nv110.fp \
+ shader/exac8nv110.fpc \
shader/exacanvc0.fp \
shader/exacanvc0.fpc \
shader/exacanve0.fp \
shader/exacanve0.fpc \
shader/exacanvf0.fp \
shader/exacanvf0.fpc \
+ shader/exacanv110.fp \
+ shader/exacanv110.fpc \
shader/exacmnvc0.fp \
shader/exacmnvc0.fpc \
shader/exacmnve0.fp \
shader/exacmnve0.fpc \
shader/exacmnvf0.fp \
shader/exacmnvf0.fpc \
+ shader/exacmnv110.fp \
+ shader/exacmnv110.fpc \
shader/exas8nvc0.fp \
shader/exas8nvc0.fpc \
shader/exas8nve0.fp \
shader/exas8nve0.fpc \
shader/exas8nvf0.fp \
shader/exas8nvf0.fpc \
+ shader/exas8nv110.fp \
+ shader/exas8nv110.fpc \
shader/exasanvc0.fp \
shader/exasanvc0.fpc \
shader/exasanve0.fp \
shader/exasanve0.fpc \
shader/exasanvf0.fp \
shader/exasanvf0.fpc \
+ shader/exasanv110.fp \
+ shader/exasanv110.fpc \
shader/exascnvc0.fp \
shader/exascnvc0.fpc \
shader/exascnve0.fp \
shader/exascnve0.fpc \
shader/exascnvf0.fp \
shader/exascnvf0.fpc \
+ shader/exascnv110.fp \
+ shader/exascnv110.fpc \
shader/videonvc0.fp \
shader/videonvc0.fpc \
shader/videonve0.fp \
shader/videonve0.fpc \
shader/videonvf0.fp \
shader/videonvf0.fpc \
+ shader/videonv110.fp \
+ shader/videonv110.fpc \
shader/xfrm2nvc0.vp \
shader/xfrm2nvc0.vpc \
shader/xfrm2nve0.vp \
shader/xfrm2nve0.vpc \
shader/xfrm2nvf0.vp \
shader/xfrm2nvf0.vpc \
+ shader/xfrm2nv110.vp \
+ shader/xfrm2nv110.vpc \
shader/Makefile \
nouveau_local.h \
nouveau_copy.h \
diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
index e152a53..c139de6 100644
--- a/src/nouveau_copy.c
+++ b/src/nouveau_copy.c
@@ -81,6 +81,7 @@ nouveau_copy_init(ScreenPtr pScreen)
&pNv->ce_channel);
break;
case NV_KEPLER:
+ case NV_MAXWELL:
ret = nouveau_object_new(&pNv->dev->object, 0,
NOUVEAU_FIFO_CHANNEL_CLASS,
&(struct nve0_fifo) {
diff --git a/src/nouveau_exa.c b/src/nouveau_exa.c
index def66ac..0f02b99 100644
--- a/src/nouveau_exa.c
+++ b/src/nouveau_exa.c
@@ -514,12 +514,12 @@ nouveau_exa_init(ScreenPtr pScreen)
break;
case NV_FERMI:
case NV_KEPLER:
+ case NV_MAXWELL:
exa->CheckComposite = NVC0EXACheckComposite;
exa->PrepareComposite = NVC0EXAPrepareComposite;
exa->Composite = NVC0EXAComposite;
exa->DoneComposite = NVC0EXADoneComposite;
break;
- case NV_MAXWELL:
default:
break;
}
diff --git a/src/nouveau_xv.c b/src/nouveau_xv.c
index d514dbf..716b18d 100644
--- a/src/nouveau_xv.c
+++ b/src/nouveau_xv.c
@@ -2142,7 +2142,7 @@ NVSetupTexturedVideo (ScreenPtr pScreen,
XF86VideoAdaptorPtr *textureAdaptor)
textureAdaptor[0] = NV40SetupTexturedVideo(pScreen, FALSE);
textureAdaptor[1] = NV40SetupTexturedVideo(pScreen, TRUE);
} else
- if (pNv->Architecture >= NV_TESLA && pNv->Architecture <
NV_MAXWELL) {
+ if (pNv->Architecture >= NV_TESLA) {
textureAdaptor[0] = NV50SetupTexturedVideo(pScreen);
}
}
diff --git a/src/nv_accel_common.c b/src/nv_accel_common.c
index 9361ce8..5d12dd8 100644
--- a/src/nv_accel_common.c
+++ b/src/nv_accel_common.c
@@ -722,6 +722,7 @@ NVAccelCommonInit(ScrnInfoPtr pScrn)
switch (pNv->Architecture) {
case NV_FERMI:
case NV_KEPLER:
+ case NV_MAXWELL:
INIT_CONTEXT_OBJECT(3D_NVC0);
break;
case NV_TESLA:
diff --git a/src/nv_driver.c b/src/nv_driver.c
index 4dde8e0..fff83f8 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -389,6 +389,7 @@ NVHasKMS(struct pci_device *pci_dev, struct
xf86_platform_device *platform_dev)
case 0xe0:
case 0xf0:
case 0x100:
+ case 0x110:
break;
default:
xf86DrvMsg(-1, X_ERROR, "Unknown chipset: NV%02X\n", chipset);
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index d2a3b93..52a17db 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -53,6 +53,16 @@
#include "shader/exas8nvf0.fp"
#include "shader/exac8nvf0.fp"
+#include "shader/xfrm2nv110.vp"
+#include "shader/videonv110.fp"
+
+#include "shader/exascnv110.fp"
+#include "shader/exacmnv110.fp"
+#include "shader/exacanv110.fp"
+#include "shader/exasanv110.fp"
+#include "shader/exas8nv110.fp"
+#include "shader/exac8nv110.fp"
+
#define NVC0PushProgram(pNv,addr,code) do {
\
const unsigned size = sizeof(code) / sizeof(code[0]); \
PUSH_DATAu((pNv)->pushbuf, (pNv)->scratch, (addr), size); \
@@ -223,9 +233,12 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
} else if (pNv->dev->chipset < 0xf0) {
class = 0xa097;
handle = 0x0000906e;
- } else {
+ } else if (pNv->dev->chipset < 0x110) {
class = 0xa197;
handle = 0x0000906e;
+ } else {
+ class = 0xb097;
+ handle = 0x0000906e;
}
ret = nouveau_object_new(pNv->channel, class, class,
@@ -304,10 +317,12 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, 1);
}
- BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
- PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
- PUSH_DATA (push, (bo->offset + MISC_OFFSET));
- PUSH_DATA (push, 1);
+ if (pNv->Architecture < NV_MAXWELL) {
+ BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
+ PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
+ PUSH_DATA (push, (bo->offset + MISC_OFFSET));
+ PUSH_DATA (push, 1);
+ }
BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
PUSH_DATA (push, (bo->offset + CODE_OFFSET) >> 32);
@@ -334,7 +349,8 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
NVC0PushProgram(pNv, PFP_S_A8, NVE0FP_Source_A8);
NVC0PushProgram(pNv, PFP_C_A8, NVE0FP_Composite_A8);
NVC0PushProgram(pNv, PFP_NV12, NVE0FP_NV12);
- } else {
+ } else
+ if (pNv->dev->chipset < 0x110) {
NVC0PushProgram(pNv, PVP_PASS, NVF0VP_Transform2);
NVC0PushProgram(pNv, PFP_S, NVF0FP_Source);
NVC0PushProgram(pNv, PFP_C, NVF0FP_Composite);
@@ -343,6 +359,15 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
NVC0PushProgram(pNv, PFP_S_A8, NVF0FP_Source_A8);
NVC0PushProgram(pNv, PFP_C_A8, NVF0FP_Composite_A8);
NVC0PushProgram(pNv, PFP_NV12, NVF0FP_NV12);
+ } else {
+ NVC0PushProgram(pNv, PVP_PASS, NV110VP_Transform2);
+ NVC0PushProgram(pNv, PFP_S, NV110FP_Source);
+ NVC0PushProgram(pNv, PFP_C, NV110FP_Composite);
+ NVC0PushProgram(pNv, PFP_CCA, NV110FP_CAComposite);
+ NVC0PushProgram(pNv, PFP_CCASA, NV110FP_CACompositeSrcAlpha);
+ NVC0PushProgram(pNv, PFP_S_A8, NV110FP_Source_A8);
+ NVC0PushProgram(pNv, PFP_C_A8, NV110FP_Composite_A8);
+ NVC0PushProgram(pNv, PFP_NV12, NV110FP_NV12);
}
BEGIN_NVC0(push, NVC0_3D(SP_SELECT(1)), 4);
diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
index 6add60b..a53dfe6 100644
--- a/src/nvc0_exa.c
+++ b/src/nvc0_exa.c
@@ -914,14 +914,56 @@ NVC0EXAComposite(PixmapPtr pdpix,
if (!PUSH_SPACE(push, 64))
return;
+ if (pNv->dev->chipset >= 0x110) {
+ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+ PUSH_DATA (push, 256);
+ PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA) >> 32);
+ PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA));
+ BEGIN_1IC0(push, NVC0_3D(CB_POS), 3 * (4 + 2 + 2) + 1);
+ PUSH_DATA (push, 0x80);
+
+ PUSH_DATAf(push, dx);
+ PUSH_DATAf(push, dy + (h * 2));
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 1);
+ PUSH_DATAf(push, sx);
+ PUSH_DATAf(push, sy + (h * 2));
+ PUSH_DATAf(push, mx);
+ PUSH_DATAf(push, my + (h * 2));
+
+ PUSH_DATAf(push, dx);
+ PUSH_DATAf(push, dy);
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 1);
+ PUSH_DATAf(push, sx);
+ PUSH_DATAf(push, sy);
+ PUSH_DATAf(push, mx);
+ PUSH_DATAf(push, my);
+
+ PUSH_DATAf(push, dx + (w * 2));
+ PUSH_DATAf(push, dy);
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 1);
+ PUSH_DATAf(push, sx + (w * 2));
+ PUSH_DATAf(push, sy);
+ PUSH_DATAf(push, mx + (w * 2));
+ PUSH_DATAf(push, my);
+ }
+
BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
PUSH_DATA (push, ((dx + w) << 16) | dx);
PUSH_DATA (push, ((dy + h) << 16) | dy);
BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
PUSH_DATA (push, NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
- PUSH_VTX2s(push, sx, sy + (h * 2), mx, my + (h * 2), dx, dy + (h * 2));
- PUSH_VTX2s(push, sx, sy, mx, my, dx, dy);
- PUSH_VTX2s(push, sx + (w * 2), sy, mx + (w * 2), my, dx + (w * 2), dy);
+ if (pNv->dev->chipset < 0x110) {
+ PUSH_VTX2s(push, sx, sy + (h * 2), mx, my + (h * 2), dx, dy + (h * 2));
+ PUSH_VTX2s(push, sx, sy, mx, my, dx, dy);
+ PUSH_VTX2s(push, sx + (w * 2), sy, mx + (w * 2), my, dx + (w * 2), dy);
+ } else {
+ BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 3);
+ }
BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 1);
PUSH_DATA (push, 0);
}
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index d1d8f18..129c505 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -247,15 +247,57 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
nouveau_pushbuf_refn (push, refs, 3))
return BadImplementation;
+ if (pNv->dev->chipset >= 0x110) {
+ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+ PUSH_DATA (push, 256);
+ PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA) >> 32);
+ PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA));
+ BEGIN_1IC0(push, NVC0_3D(CB_POS), 3 * (4 + 2 + 2) + 1);
+ PUSH_DATA (push, 0x80);
+
+ PUSH_DATAf(push, sx1);
+ PUSH_DATAf(push, sy1);
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 1);
+ PUSH_DATAf(push, tx1);
+ PUSH_DATAf(push, ty1);
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 0);
+
+ PUSH_DATAf(push, sx2+(sx2-sx1));
+ PUSH_DATAf(push, sy1);
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 1);
+ PUSH_DATAf(push, tx2+(tx2-tx1));
+ PUSH_DATAf(push, ty1);
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 0);
+
+ PUSH_DATAf(push, sx1);
+ PUSH_DATAf(push, sy2+(sy2-sy1));
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 1);
+ PUSH_DATAf(push, tx1);
+ PUSH_DATAf(push, ty2+(ty2-ty1));
+ PUSH_DATAf(push, 0);
+ PUSH_DATAf(push, 0);
+ }
+
BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
PUSH_DATA (push, sx2 << NVC0_3D_SCISSOR_HORIZ_MAX__SHIFT | sx1);
PUSH_DATA (push, sy2 << NVC0_3D_SCISSOR_VERT_MAX__SHIFT | sy1 );
BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
PUSH_DATA (push, NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
- PUSH_VTX1s(push, tx1, ty1, sx1, sy1);
- PUSH_VTX1s(push, tx2+(tx2-tx1), ty1, sx2+(sx2-sx1), sy1);
- PUSH_VTX1s(push, tx1, ty2+(ty2-ty1), sx1, sy2+(sy2-sy1));
+ if (pNv->dev->chipset < 0x110) {
+ PUSH_VTX1s(push, tx1, ty1, sx1, sy1);
+ PUSH_VTX1s(push, tx2+(tx2-tx1), ty1, sx2+(sx2-sx1), sy1);
+ PUSH_VTX1s(push, tx1, ty2+(ty2-ty1), sx1, sy2+(sy2-sy1));
+ } else {
+ BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 3);
+ }
BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 1);
PUSH_DATA (push, 0);
diff --git a/src/shader/Makefile b/src/shader/Makefile
index 2d789be..12bf455 100644
--- a/src/shader/Makefile
+++ b/src/shader/Makefile
@@ -22,23 +22,36 @@ NVF0_SHADERS = xfrm2nvf0.vpc \
exas8nvf0.fpc \
exac8nvf0.fpc \
videonvf0.fpc
+NV110_SHADERS = xfrm2nv110.vpc \
+ exascnv110.fpc \
+ exacmnv110.fpc \
+ exacanv110.fpc \
+ exasanv110.fpc \
+ exas8nv110.fpc \
+ exac8nv110.fpc \
+ videonv110.fpc
-SHADERS = $(NVC0_SHADERS) $(NVE0_SHADERS) $(NVF0_SHADERS)
+SHADERS = $(NVC0_SHADERS) $(NVE0_SHADERS) $(NVF0_SHADERS) $(NV110_SHADERS)
ENVYAS ?= envyas
all: $(SHADERS)
$(filter %nvc0.vpc,$(SHADERS)): %.vpc: %.vp
- cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -o $@
+ cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gf100 -V gf100
-o $@
$(filter %nvc0.fpc,$(SHADERS)): %.fpc: %.fp
- cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -o $@
+ cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gf100 -V gf100
-o $@
$(filter %nve0.vpc,$(SHADERS)): %.vpc: %.vp
- cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -V nve4 -o
$@
+ cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gf100 -V gk104
-o $@
$(filter %nve0.fpc,$(SHADERS)): %.fpc: %.fp
- cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -V nve4 -o
$@
+ cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gf100 -V gk104
-o $@
$(filter %nvf0.vpc,$(SHADERS)): %.vpc: %.vp
cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gk110 -o $@
$(filter %nvf0.fpc,$(SHADERS)): %.fpc: %.fp
cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gk110 -o $@
+
+$(filter %nv110.vpc,$(SHADERS)): %.vpc: %.vp
+ cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gm107 -o $@
+$(filter %nv110.fpc,$(SHADERS)): %.fpc: %.fp
+ cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gm107 -o $@
diff --git a/src/shader/exac8nv110.fp b/src/shader/exac8nv110.fp
new file mode 100644
index 0000000..ce78036
--- /dev/null
+++ b/src/shader/exac8nv110.fp
@@ -0,0 +1,47 @@
+#ifndef ENVYAS
+static uint32_t
+NV110FP_Composite_A8[] = {
+ 0x00001462,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80000000,
+ 0x00000a0a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000f,
+ 0x00000000,
+#include "exac8nv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r3 a[0x94] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x90] $r0 0x0 0x1
+tex nodep $r1 $r2 0x0 0x1 t2d 0x8
+ipa $r3 a[0x84] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x80] $r0 0x0 0x1
+tex nodep $r0 $r2 0x0 0x0 t2d 0x8
+depbar le 0x5 0x0 0x0
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r3 $r0 $r1
+mov $r2 $r3 0xf
+mov $r1 $r3 0xf
+sched (st 0x0) (st 0x0) (st 0x0)
+mov $r0 $r3 0xf
+exit
+#endif
diff --git a/src/shader/exac8nv110.fpc b/src/shader/exac8nv110.fpc
new file mode 100644
index 0000000..4aa1368
--- /dev/null
+++ b/src/shader/exac8nv110.fpc
@@ -0,0 +1,38 @@
+0xfc0007e0,
+0x001f8000,
+0xcff7ff00,
+0xe003ff87,
+0x00470000,
+0x50800000,
+0x4007ff03,
+0xe043ff89,
+0xfc0007e0,
+0x001f8000,
+0x0007ff02,
+0xe043ff89,
+0x2ff70201,
+0xc03a0014,
+0x4007ff03,
+0xe043ff88,
+0xfc0007e0,
+0x001f8000,
+0x0007ff02,
+0xe043ff88,
+0x2ff70200,
+0xc03a0004,
+0x34070000,
+0xf0f00000,
+0xfc0007e0,
+0x001f8000,
+0x00170003,
+0x5c681000,
+0x00370002,
+0x5c980780,
+0x00370001,
+0x5c980780,
+0xfc0007e0,
+0x001f8000,
+0x00370000,
+0x5c980780,
+0x0007000f,
+0xe3000000,
diff --git a/src/shader/exacanv110.fp b/src/shader/exacanv110.fp
new file mode 100644
index 0000000..a70d5c5
--- /dev/null
+++ b/src/shader/exacanv110.fp
@@ -0,0 +1,47 @@
+#ifndef ENVYAS
+static uint32_t
+NV110FP_CAComposite[] = {
+ 0x00001462, /* 0x0000c000 = USES_KIL, MULTI_COLORS */
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80000000, /* FRAG_COORD_UMASK = 0x8 */
+ 0x00000a0a, /* FP_INTERP[0x080], 0022 0022 */
+ 0x00000000, /* FP_INTERP[0x0c0], 0 = OFF */
+ 0x00000000, /* FP_INTERP[0x100], 1 = FLAT */
+ 0x00000000, /* FP_INTERP[0x140], 2 = PERSPECTIVE */
+ 0x00000000, /* FP_INTERP[0x180], 3 = LINEAR */
+ 0x00000000, /* FP_INTERP[0x1c0] */
+ 0x00000000, /* FP_INTERP[0x200] */
+ 0x00000000, /* FP_INTERP[0x240] */
+ 0x00000000, /* FP_INTERP[0x280] */
+ 0x00000000, /* FP_INTERP[0x2c0] */
+ 0x00000000, /* FP_INTERP[0x300] */
+ 0x00000000,
+ 0x0000000f, /* FP_RESULT_MASK (0x8000 Face ?) */
+ 0x00000000, /* 0x2 = FragDepth, 0x1 = SampleMask */
+#include "exacanv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r3 a[0x94] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x90] $r0 0x0 0x1
+tex nodep $r4 $r2 0x0 0x1 t2d 0xf
+ipa $r1 a[0x84] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r0 a[0x80] $r0 0x0 0x1
+tex nodep $r0 $r0 0x0 0x0 t2d 0xf
+depbar le 0x5 0x0 0x0
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r3 $r3 $r7
+fmul ftz $r2 $r2 $r6
+fmul ftz $r1 $r1 $r5
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r0 $r0 $r4
+exit
+#endif
diff --git a/src/shader/exacanv110.fpc b/src/shader/exacanv110.fpc
new file mode 100644
index 0000000..7c0ca5e
--- /dev/null
+++ b/src/shader/exacanv110.fpc
@@ -0,0 +1,38 @@
+0xfc0007e0,
+0x001f8000,
+0xcff7ff00,
+0xe003ff87,
+0x00470000,
+0x50800000,
+0x4007ff03,
+0xe043ff89,
+0xfc0007e0,
+0x001f8000,
+0x0007ff02,
+0xe043ff89,
+0xaff70204,
+0xc03a0017,
+0x4007ff01,
+0xe043ff88,
+0xfc0007e0,
+0x001f8000,
+0x0007ff00,
+0xe043ff88,
+0xaff70000,
+0xc03a0007,
+0x34070000,
+0xf0f00000,
+0xfc0007e0,
+0x001f8000,
+0x00770303,
+0x5c681000,
+0x00670202,
+0x5c681000,
+0x00570101,
+0x5c681000,
+0xfc0007e0,
+0x001f8000,
+0x00470000,
+0x5c681000,
+0x0007000f,
+0xe3000000,
diff --git a/src/shader/exacmnv110.fp b/src/shader/exacmnv110.fp
new file mode 100644
index 0000000..fe5c294
--- /dev/null
+++ b/src/shader/exacmnv110.fp
@@ -0,0 +1,47 @@
+#ifndef ENVYAS
+static uint32_t
+NV110FP_Composite[] = {
+ 0x00001462,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80000000,
+ 0x00000a0a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000f,
+ 0x00000000,
+#include "exacmnv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r3 a[0x94] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x90] $r0 0x0 0x1
+tex nodep $r4 $r2 0x0 0x1 t2d 0x8
+ipa $r1 a[0x84] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r0 a[0x80] $r0 0x0 0x1
+tex nodep $r0 $r0 0x0 0x0 t2d 0xf
+depbar le 0x5 0x0 0x0
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r3 $r3 $r4
+fmul ftz $r2 $r2 $r4
+fmul ftz $r1 $r1 $r4
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r0 $r0 $r4
+exit
+#endif
diff --git a/src/shader/exacmnv110.fpc b/src/shader/exacmnv110.fpc
new file mode 100644
index 0000000..9d62c1a
--- /dev/null
+++ b/src/shader/exacmnv110.fpc
@@ -0,0 +1,38 @@
+0xfc0007e0,
+0x001f8000,
+0xcff7ff00,
+0xe003ff87,
+0x00470000,
+0x50800000,
+0x4007ff03,
+0xe043ff89,
+0xfc0007e0,
+0x001f8000,
+0x0007ff02,
+0xe043ff89,
+0x2ff70204,
+0xc03a0014,
+0x4007ff01,
+0xe043ff88,
+0xfc0007e0,
+0x001f8000,
+0x0007ff00,
+0xe043ff88,
+0xaff70000,
+0xc03a0007,
+0x34070000,
+0xf0f00000,
+0xfc0007e0,
+0x001f8000,
+0x00470303,
+0x5c681000,
+0x00470202,
+0x5c681000,
+0x00470101,
+0x5c681000,
+0xfc0007e0,
+0x001f8000,
+0x00470000,
+0x5c681000,
+0x0007000f,
+0xe3000000,
diff --git a/src/shader/exas8nv110.fp b/src/shader/exas8nv110.fp
new file mode 100644
index 0000000..4fe2e19
--- /dev/null
+++ b/src/shader/exas8nv110.fp
@@ -0,0 +1,42 @@
+#ifndef ENVYAS
+static uint32_t
+NV110FP_Source_A8[] = {
+ 0x00001462,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80000000,
+ 0x0000000a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000f,
+ 0x00000000,
+#include "exas8nv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r1 a[0x84] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r0 a[0x80] $r0 0x0 0x1
+tex nodep $r0 $r0 0x0 0x0 t2d 0x8
+depbar le 0x5 0x0 0x0
+sched (st 0x0) (st 0x0) (st 0x0)
+mov $r3 $r0 0xf
+mov $r2 $r0 0xf
+mov $r1 $r0 0xf
+sched (st 0x0) (st 0x0) (st 0x0)
+exit
+#endif
diff --git a/src/shader/exas8nv110.fpc b/src/shader/exas8nv110.fpc
new file mode 100644
index 0000000..1181c41
--- /dev/null
+++ b/src/shader/exas8nv110.fpc
@@ -0,0 +1,28 @@
+0xfc0007e0,
+0x001f8000,
+0xcff7ff00,
+0xe003ff87,
+0x00470000,
+0x50800000,
+0x4007ff01,
+0xe043ff88,
+0xfc0007e0,
+0x001f8000,
+0x0007ff00,
+0xe043ff88,
+0x2ff70000,
+0xc03a0004,
+0x34070000,
+0xf0f00000,
+0xfc0007e0,
+0x001f8000,
+0x00070003,
+0x5c980780,
+0x00070002,
+0x5c980780,
+0x00070001,
+0x5c980780,
+0xfc0007e0,
+0x001f8000,
+0x0007000f,
+0xe3000000,
diff --git a/src/shader/exasanv110.fp b/src/shader/exasanv110.fp
new file mode 100644
index 0000000..61374a6
--- /dev/null
+++ b/src/shader/exasanv110.fp
@@ -0,0 +1,47 @@
+#ifndef ENVYAS
+static uint32_t
+NV110FP_CACompositeSrcAlpha[] = {
+ 0x00001462,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80000000,
+ 0x00000a0a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000f,
+ 0x00000000,
+#include "exasanv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r3 a[0x84] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x80] $r0 0x0 0x1
+tex nodep $r4 $r2 0x0 0x0 t2d 0x8
+ipa $r1 a[0x94] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r0 a[0x90] $r0 0x0 0x1
+tex nodep $r0 $r0 0x0 0x1 t2d 0xf
+depbar le 0x5 0x0 0x0
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r3 $r3 $r4
+fmul ftz $r2 $r2 $r4
+fmul ftz $r1 $r1 $r4
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r0 $r0 $r4
+exit
+#endif
diff --git a/src/shader/exasanv110.fpc b/src/shader/exasanv110.fpc
new file mode 100644
index 0000000..5516a03
--- /dev/null
+++ b/src/shader/exasanv110.fpc
@@ -0,0 +1,38 @@
+0xfc0007e0,
+0x001f8000,
+0xcff7ff00,
+0xe003ff87,
+0x00470000,
+0x50800000,
+0x4007ff03,
+0xe043ff88,
+0xfc0007e0,
+0x001f8000,
+0x0007ff02,
+0xe043ff88,
+0x2ff70204,
+0xc03a0004,
+0x4007ff01,
+0xe043ff89,
+0xfc0007e0,
+0x001f8000,
+0x0007ff00,
+0xe043ff89,
+0xaff70000,
+0xc03a0017,
+0x34070000,
+0xf0f00000,
+0xfc0007e0,
+0x001f8000,
+0x00470303,
+0x5c681000,
+0x00470202,
+0x5c681000,
+0x00470101,
+0x5c681000,
+0xfc0007e0,
+0x001f8000,
+0x00470000,
+0x5c681000,
+0x0007000f,
+0xe3000000,
diff --git a/src/shader/exascnv110.fp b/src/shader/exascnv110.fp
new file mode 100644
index 0000000..90bbb55
--- /dev/null
+++ b/src/shader/exascnv110.fp
@@ -0,0 +1,38 @@
+#ifndef ENVYAS
+static uint32_t
+NV110FP_Source[] = {
+ 0x00001462,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80000000,
+ 0x0000000a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000f,
+ 0x00000000,
+#include "exascnv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r1 a[0x84] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r0 a[0x80] $r0 0x0 0x1
+tex nodep $r0 $r0 0x0 0x0 t2d 0xf
+depbar le 0x5 0x0 0x0
+sched (st 0x0) (st 0x0) (st 0x0)
+exit
+#endif
diff --git a/src/shader/exascnv110.fpc b/src/shader/exascnv110.fpc
new file mode 100644
index 0000000..2dba15d
--- /dev/null
+++ b/src/shader/exascnv110.fpc
@@ -0,0 +1,20 @@
+0xfc0007e0,
+0x001f8000,
+0xcff7ff00,
+0xe003ff87,
+0x00470000,
+0x50800000,
+0x4007ff01,
+0xe043ff88,
+0xfc0007e0,
+0x001f8000,
+0x0007ff00,
+0xe043ff88,
+0xaff70000,
+0xc03a0007,
+0x34070000,
+0xf0f00000,
+0xfc0007e0,
+0x001f8000,
+0x0007000f,
+0xe3000000,
diff --git a/src/shader/videonv110.fp b/src/shader/videonv110.fp
new file mode 100644
index 0000000..2728311
--- /dev/null
+++ b/src/shader/videonv110.fp
@@ -0,0 +1,54 @@
+#ifndef ENVYAS
+static uint32_t
+NV110FP_NV12[] = {
+ 0x00001462,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80000000,
+ 0x0000000a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000f,
+ 0x00000000,
+#include "videonv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r2 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r2 $r2
+ipa $r0 a[0x80] $r2 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r1 a[0x84] $r2 0x0 0x1
+tex nodep $r4 $r0 0x0 0x0 t2d 0x8
+tex nodep $r0 $r0 0x0 0x1 t2d 0xc
+sched (st 0x0) (st 0x0) (st 0x0)
+depbar le 0x5 0x1 0x1
+fmul ftz $r5 $r4 c0[0x0]
+fadd ftz $r3 $r5 c0[0x4]
+sched (st 0x0) (st 0x0) (st 0x0)
+fadd ftz $r4 $r5 c0[0x8]
+fadd ftz $r5 $r5 c0[0xc]
+depbar le 0x5 0x0 0x0
+sched (st 0x0) (st 0x0) (st 0x0)
+ffma ftz $r3 $r0 c0[0x10] $r3
+ffma ftz $r4 $r0 c0[0x14] $r4
+ffma ftz $r5 $r0 c0[0x18] $r5
+sched (st 0x0) (st 0x0) (st 0x0)
+ffma ftz $r0 $r1 c0[0x1c] $r3
+ffma ftz $r2 $r1 c0[0x24] $r5
+ffma ftz $r1 $r1 c0[0x20] $r4
+sched (st 0x0) (st 0x0) (st 0x0)
+exit
+#endif
diff --git a/src/shader/videonv110.fpc b/src/shader/videonv110.fpc
new file mode 100644
index 0000000..31d745a
--- /dev/null
+++ b/src/shader/videonv110.fpc
@@ -0,0 +1,52 @@
+0xfc0007e0,
+0x001f8000,
+0xcff7ff02,
+0xe003ff87,
+0x00470202,
+0x50800000,
+0x0027ff00,
+0xe043ff88,
+0xfc0007e0,
+0x001f8000,
+0x4027ff01,
+0xe043ff88,
+0x2ff70004,
+0xc03a0004,
+0x2ff70000,
+0xc03a0016,
+0xfc0007e0,
+0x001f8000,
+0x34170001,
+0xf0f00000,
+0x00070405,
+0x4c681000,
+0x00170503,
+0x4c581000,
+0xfc0007e0,
+0x001f8000,
+0x00270504,
+0x4c581000,
+0x00370505,
+0x4c581000,
+0x34070000,
+0xf0f00000,
+0xfc0007e0,
+0x001f8000,
+0x00470003,
+0x49a00180,
+0x00570004,
+0x49a00200,
+0x00670005,
+0x49a00280,
+0xfc0007e0,
+0x001f8000,
+0x00770100,
+0x49a00180,
+0x00970102,
+0x49a00280,
+0x00870101,
+0x49a00200,
+0xfc0007e0,
+0x001f8000,
+0x0007000f,
+0xe3000000,
diff --git a/src/shader/xfrm2nv110.vp b/src/shader/xfrm2nv110.vp
new file mode 100644
index 0000000..bbfc527
--- /dev/null
+++ b/src/shader/xfrm2nv110.vp
@@ -0,0 +1,82 @@
+#ifndef ENVYAS
+static uint32_t
+NV110VP_Transform2[] = {
+ 0x02000461,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x000ff000,
+ 0x00000000, /* VP_ATTR_EN[0x000] */
+ 0x00000000, /* VP_ATTR_EN[0x080] */
+ 0x00000000, /* VP_ATTR_EN[0x100] */
+ 0x00000000,
+ 0x00000000, /* VP_ATTR_EN[0x200] */
+ 0x80000000, /* VERTEXID */
+ 0x00000000, /* VP_ATTR_EN[0x300] */
+ 0x00000000,
+ 0x0033f000, /* VP_EXPORT_EN[0x040] */
+ 0x00000000, /* VP_EXPORT_EN[0x0c0] */
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000, /* VP_EXPORT_EN[0x2c0] */
+ 0x00000000,
+#include "xfrm2nv110.vpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ld b32 $r5 a[0x2fc] 0x0
+shl $r5 $r5 0x5
+ld b64 $r0 c0[$r5+0x80]
+sched (st 0x0) (st 0x0) (st 0x0)
+ld b64 $r2 c0[$r5+0x88]
+st b128 a[0x70] $r0 0x0
+
+ld b64 $r0 c0[$r5+0x90]
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r2 $r0 c0[0x0]
+fmul ftz $r3 $r0 c0[0xc]
+fmul ftz $r4 $r0 c0[0x18]
+sched (st 0x0) (st 0x0) (st 0x0)
+ffma ftz $r2 $r1 c0[0x4] $r2
+ffma ftz $r3 $r1 c0[0x10] $r3
+ffma ftz $r4 $r1 c0[0x1c] $r4
+sched (st 0x0) (st 0x0) (st 0x0)
+fadd ftz $r2 $r2 c0[0x8]
+fadd ftz $r3 $r3 c0[0x14]
+fadd ftz $r4 $r4 c0[0x20]
+sched (st 0x0) (st 0x0) (st 0x0)
+mufu rcp $r4 $r4
+fmul ftz $r2 $r2 $r4
+fmul ftz $r3 $r3 $r4
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r0 $r2 c0[0x24]
+fmul ftz $r1 $r3 c0[0x28]
+st b64 a[0x80] $r0 0x0
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ld b64 $r0 c0[$r5+0x98]
+fmul ftz $r2 $r0 c0[0x2c]
+fmul ftz $r3 $r0 c0[0x38]
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r4 $r0 c0[0x44]
+ffma ftz $r2 $r1 c0[0x30] $r2
+ffma ftz $r3 $r1 c0[0x3c] $r3
+sched (st 0x0) (st 0x0) (st 0x0)
+ffma ftz $r4 $r1 c0[0x48] $r4
+fadd ftz $r2 $r2 c0[0x34]
+fadd ftz $r3 $r3 c0[0x40]
+sched (st 0x0) (st 0x0) (st 0x0)
+fadd ftz $r4 $r4 c0[0x4c]
+mufu rcp $r4 $r4
+fmul ftz $r2 $r2 $r4
+sched (st 0x0) (st 0x0) (st 0x0)
+fmul ftz $r3 $r3 $r4
+fmul ftz $r0 $r2 c0[0x50]
+fmul ftz $r1 $r3 c0[0x54]
+sched (st 0x0) (st 0x0) (st 0x0)
+st b64 a[0x90] $r0 0x0
+
+exit
+#endif
diff --git a/src/shader/xfrm2nv110.vpc b/src/shader/xfrm2nv110.vpc
new file mode 100644
index 0000000..0d9ebfd
--- /dev/null
+++ b/src/shader/xfrm2nv110.vpc
@@ -0,0 +1,102 @@
+0xfc0007e0,
+0x001f8000,
+0x2fc7ff05,
+0xefd87f80,
+0x00570505,
+0x38480000,
+0x08070500,
+0xef950000,
+0xfc0007e0,
+0x001f8000,
+0x08870502,
+0xef950000,
+0x0707ff00,
+0xeff1ff80,
+0x09070500,
+0xef950000,
+0xfc0007e0,
+0x001f8000,
+0x00070002,
+0x4c681000,
+0x00370003,
+0x4c681000,
+0x00670004,
+0x4c681000,
+0xfc0007e0,
+0x001f8000,
+0x00170102,
+0x49a00100,
+0x00470103,
+0x49a00180,
+0x00770104,
+0x49a00200,
+0xfc0007e0,
+0x001f8000,
+0x00270202,
+0x4c581000,
+0x00570303,
+0x4c581000,
+0x00870404,
+0x4c581000,
+0xfc0007e0,
+0x001f8000,
+0x00470404,
+0x50800000,
+0x00470202,
+0x5c681000,
+0x00470303,
+0x5c681000,
+0xfc0007e0,
+0x001f8000,
+0x00970200,
+0x4c681000,
+0x00a70301,
+0x4c681000,
+0x0807ff00,
+0xeff0ff80,
+0xfc0007e0,
+0x001f8000,
+0x09870500,
+0xef950000,
+0x00b70002,
+0x4c681000,
+0x00e70003,
+0x4c681000,
+0xfc0007e0,
+0x001f8000,
+0x01170004,
+0x4c681000,
+0x00c70102,
+0x49a00100,
+0x00f70103,
+0x49a00180,
+0xfc0007e0,
+0x001f8000,
+0x01270104,
+0x49a00200,
+0x00d70202,
+0x4c581000,
+0x01070303,
+0x4c581000,
+0xfc0007e0,
+0x001f8000,
+0x01370404,
+0x4c581000,
+0x00470404,
+0x50800000,
+0x00470202,
+0x5c681000,
+0xfc0007e0,
+0x001f8000,
+0x00470303,
+0x5c681000,
+0x01470200,
+0x4c681000,
+0x01570301,
+0x4c681000,
+0xfc0007e0,
+0x001f8000,
+0x0907ff00,
+0xeff0ff80,
+0x0007000f,
+0xe3000000,
--
2.7.3
Ilia Mirkin
2016-Oct-27 14:02 UTC
[Nouveau] [PATCH v2 2/7] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Acked-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> --- src/Makefile.am | 1 + src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++ src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++---------------- 3 files changed, 893 insertions(+), 340 deletions(-) create mode 100644 src/hwdefs/gm107_texture.xml.h diff --git a/src/Makefile.am b/src/Makefile.am index 6ba8d87..d777fe5 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -71,6 +71,7 @@ EXTRA_DIST = hwdefs/nv_3ddefs.xml.h \ hwdefs/nv50_texture.h \ hwdefs/nvc0_3d.xml.h \ hwdefs/nvc0_m2mf.xml.h \ + hwdefs/gm107_texture.xml.h \ shader/exac8nvc0.fp \ shader/exac8nvc0.fpc \ shader/exac8nve0.fp \ diff --git a/src/hwdefs/gm107_texture.xml.h b/src/hwdefs/gm107_texture.xml.h new file mode 100644 index 0000000..a4bc380 --- /dev/null +++ b/src/hwdefs/gm107_texture.xml.h @@ -0,0 +1,365 @@ +#ifndef GM107_TEXTURE_XML +#define GM107_TEXTURE_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/envytools/envytools/ +git clone https://github.com/envytools/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/skeggsb/git/envytools/rnndb/../rnndb/graph/gm107_texture.xml ( 22057 bytes, from 2016-02-12 03:01:43) +- /home/skeggsb/git/envytools/rnndb/copyright.xml ( 6456 bytes, from 2015-09-10 02:57:40) +- /home/skeggsb/git/envytools/rnndb/nvchipsets.xml ( 2908 bytes, from 2016-02-04 22:19:11) +- /home/skeggsb/git/envytools/rnndb/g80_defs.xml ( 21739 bytes, from 2016-02-04 00:29:42) + +Copyright (C) 2006-2016 by the following authors: +- Artur Huillet <arthur.huillet at free.fr> (ahuillet) +- Ben Skeggs (darktama, darktama_) +- B. R. <koala_br at users.sourceforge.net> (koala_br) +- Carlos Martin <carlosmn at users.sf.net> (carlosmn) +- Christoph Bumiller <e0425955 at student.tuwien.ac.at> (calim, chrisbmr) +- Dawid Gajownik <gajownik at users.sf.net> (gajownik) +- Dmitry Baryshkov +- Dmitry Eremin-Solenikov <lumag at users.sf.net> (lumag) +- EdB <edb_ at users.sf.net> (edb_) +- Erik Waling <erikwailing at users.sf.net> (erikwaling) +- Francisco Jerez <currojerez at riseup.net> (curro) +- Ilia Mirkin <imirkin at alum.mit.edu> (imirkin) +- jb17bsome <jb17bsome at bellsouth.net> (jb17bsome) +- Jeremy Kolb <kjeremy at users.sf.net> (kjeremy) +- Laurent Carlier <lordheavym at gmail.com> (lordheavy) +- Luca Barbieri <luca at luca-barbieri.com> (lb, lb1) +- Maarten Maathuis <madman2003 at gmail.com> (stillunknown) +- Marcin Kościelnicki <koriakin at 0x04.net> (mwk, koriakin) +- Mark Carey <mark.carey at gmail.com> (careym) +- Matthieu Castet <matthieu.castet at parrot.com> (mat-c) +- nvidiaman <nvidiaman at users.sf.net> (nvidiaman) +- Patrice Mandin <patmandin at gmail.com> (pmandin, pmdata) +- Pekka Paalanen <pq at iki.fi> (pq, ppaalanen) +- Peter Popov <ironpeter at users.sf.net> (ironpeter) +- Richard Hughes <hughsient at users.sf.net> (hughsient) +- Rudi Cilibrasi <cilibrar at users.sf.net> (cilibrar) +- Serge Martin +- Simon Raffeiner +- Stephane Loeuillet <leroutier at users.sf.net> (leroutier) +- Stephane Marchesin <stephane.marchesin at gmail.com> (marcheu) +- sturmflut <sturmflut at users.sf.net> (sturmflut) +- Sylvain Munaut <tnt at 246tNt.com> +- Victor Stinner <victor.stinner at haypocalc.com> (haypo) +- Wladmir van der Laan <laanwj at gmail.com> (miathan6) +- Younes Manton <younes.m at gmail.com> (ymanton) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define GM107_TIC2__SIZE 0x00000020 +#define GM107_TIC2_0 0x00000000 +#define GM107_TIC2_0_COMPONENTS_SIZES__MASK 0x0000007f +#define GM107_TIC2_0_COMPONENTS_SIZES__SHIFT 0 +#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define GM107_TIC2_0_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32 0x00000004 +#define GM107_TIC2_0_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define GM107_TIC2_0_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define GM107_TIC2_0_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define GM107_TIC2_0_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define GM107_TIC2_0_COMPONENTS_SIZES_R16_G16 0x0000000c +#define GM107_TIC2_0_COMPONENTS_SIZES_G8R24 0x0000000d +#define GM107_TIC2_0_COMPONENTS_SIZES_G24R8 0x0000000e +#define GM107_TIC2_0_COMPONENTS_SIZES_R32 0x0000000f +#define GM107_TIC2_0_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define GM107_TIC2_0_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define GM107_TIC2_0_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define GM107_TIC2_0_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define GM107_TIC2_0_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define GM107_TIC2_0_COMPONENTS_SIZES_G8R8 0x00000018 +#define GM107_TIC2_0_COMPONENTS_SIZES_R16 0x0000001b +#define GM107_TIC2_0_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define GM107_TIC2_0_COMPONENTS_SIZES_R8 0x0000001d +#define GM107_TIC2_0_COMPONENTS_SIZES_G4R4 0x0000001e +#define GM107_TIC2_0_COMPONENTS_SIZES_R1 0x0000001f +#define GM107_TIC2_0_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define GM107_TIC2_0_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define GM107_TIC2_0_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define GM107_TIC2_0_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define GM107_TIC2_0_COMPONENTS_SIZES_DXT1 0x00000024 +#define GM107_TIC2_0_COMPONENTS_SIZES_DXT23 0x00000025 +#define GM107_TIC2_0_COMPONENTS_SIZES_DXT45 0x00000026 +#define GM107_TIC2_0_COMPONENTS_SIZES_DXN1 0x00000027 +#define GM107_TIC2_0_COMPONENTS_SIZES_DXN2 0x00000028 +#define GM107_TIC2_0_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define GM107_TIC2_0_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define GM107_TIC2_0_COMPONENTS_SIZES_BC7U 0x00000017 +#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define GM107_TIC2_0_COMPONENTS_SIZES_EAC 0x00000019 +#define GM107_TIC2_0_COMPONENTS_SIZES_EACX2 0x0000001a +#define GM107_TIC2_0_COMPONENTS_SIZES_Z24S8 0x00000029 +#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24 0x0000002a +#define GM107_TIC2_0_COMPONENTS_SIZES_S8Z24 0x0000002b +#define GM107_TIC2_0_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define GM107_TIC2_0_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define GM107_TIC2_0_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32 0x0000002f +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define GM107_TIC2_0_COMPONENTS_SIZES_Z16 0x0000003a +#define GM107_TIC2_0_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define GM107_TIC2_0_R_DATA_TYPE__MASK 0x00000380 +#define GM107_TIC2_0_R_DATA_TYPE__SHIFT 7 +#define GM107_TIC2_0_G_DATA_TYPE__MASK 0x00001c00 +#define GM107_TIC2_0_G_DATA_TYPE__SHIFT 10 +#define GM107_TIC2_0_B_DATA_TYPE__MASK 0x0000e000 +#define GM107_TIC2_0_B_DATA_TYPE__SHIFT 13 +#define GM107_TIC2_0_A_DATA_TYPE__MASK 0x00070000 +#define GM107_TIC2_0_A_DATA_TYPE__SHIFT 16 +#define GM107_TIC2_0_X_SOURCE__MASK 0x00380000 +#define GM107_TIC2_0_X_SOURCE__SHIFT 19 +#define GM107_TIC2_0_Y_SOURCE__MASK 0x01c00000 +#define GM107_TIC2_0_Y_SOURCE__SHIFT 22 +#define GM107_TIC2_0_Z_SOURCE__MASK 0x0e000000 +#define GM107_TIC2_0_Z_SOURCE__SHIFT 25 +#define GM107_TIC2_0_W_SOURCE__MASK 0x70000000 +#define GM107_TIC2_0_W_SOURCE__SHIFT 28 +#define GM107_TIC2_0_PACK_COMPONENTS 0x80000000 + +#define GM107_TIC2_1 0x00000004 +#define GM107_TIC2_1_ADDRESS_BITS_31_TO_0__MASK 0xffffffff +#define GM107_TIC2_1_ADDRESS_BITS_31_TO_0__SHIFT 0 +#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__MASK 0xffffffe0 +#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__SHIFT 5 +#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__SHR 5 +#define GM107_TIC2_1_GOB_DEPTH_OFFSET__MASK 0x00000060 +#define GM107_TIC2_1_GOB_DEPTH_OFFSET__SHIFT 5 +#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__MASK 0xfffffe00 +#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__SHIFT 9 +#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__SHR 9 + +#define GM107_TIC2_2 0x00000008 +#define GM107_TIC2_2_ADDRESS_BITS_47_TO_32__MASK 0x0000ffff +#define GM107_TIC2_2_ADDRESS_BITS_47_TO_32__SHIFT 0 +#define GM107_TIC2_2_HEADER_VERSION__MASK 0x00e00000 +#define GM107_TIC2_2_HEADER_VERSION__SHIFT 21 +#define GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER 0x00000000 +#define GM107_TIC2_2_HEADER_VERSION_PITCH_COLORKEY 0x00200000 +#define GM107_TIC2_2_HEADER_VERSION_PITCH 0x00400000 +#define GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR 0x00600000 +#define GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR_COLORKEY 0x00800000 +#define GM107_TIC2_2_RESOURCE_VIEW_COHERENCY_HASH__MASK 0x1e000000 +#define GM107_TIC2_2_RESOURCE_VIEW_COHERENCY_HASH__SHIFT 25 + +#define GM107_TIC2_3 0x0000000c +#define GM107_TIC2_3_WIDTH_MINUS_ONE_BITS_31_TO_16__MASK 0x0000ffff +#define GM107_TIC2_3_WIDTH_MINUS_ONE_BITS_31_TO_16__SHIFT 0 +#define GM107_TIC2_3_PITCH_BITS_20_TO_5__MASK 0x0000ffff +#define GM107_TIC2_3_PITCH_BITS_20_TO_5__SHIFT 0 +#define GM107_TIC2_3_PITCH_BITS_20_TO_5__SHR 5 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MASK 0x00000007 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__SHIFT 0 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MIN 0x00000000 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MAX 0x00000000 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_ONE 0x00000000 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_TWO 0x00000001 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_FOUR 0x00000002 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_EIGHT 0x00000003 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_SIXTEEN 0x00000004 +#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_THIRTYTWO 0x00000005 +#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT__MASK 0x00000038 +#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT__SHIFT 3 +#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_ONE 0x00000000 +#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_TWO 0x00000008 +#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_FOUR 0x00000010 +#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_EIGHT 0x00000018 +#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_SIXTEEN 0x00000020 +#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO 0x00000028 +#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH__MASK 0x000001c0 +#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH__SHIFT 6 +#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_ONE 0x00000000 +#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_TWO 0x00000040 +#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_FOUR 0x00000080 +#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_EIGHT 0x000000c0 +#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_SIXTEEN 0x00000100 +#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_THIRTYTWO 0x00000140 +#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS__MASK 0x00001c00 +#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS__SHIFT 10 +#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_ONE 0x00000000 +#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_TWO 0x00000400 +#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_FOUR 0x00000800 +#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_EIGHT 0x00000c00 +#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_SIXTEEN 0x00001000 +#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_THIRTYTWO 0x00001400 +#define GM107_TIC2_3_GOB_3D 0x00002000 +#define GM107_TIC2_3_LOD_ANISO_QUALITY_2 0x00010000 +#define GM107_TIC2_3_LOD_ANISO_QUALITY__MASK 0x00020000 +#define GM107_TIC2_3_LOD_ANISO_QUALITY__SHIFT 17 +#define GM107_TIC2_3_LOD_ANISO_QUALITY_LOW 0x00000000 +#define GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH 0x00020000 +#define GM107_TIC2_3_LOD_ISO_QUALITY__MASK 0x00040000 +#define GM107_TIC2_3_LOD_ISO_QUALITY__SHIFT 18 +#define GM107_TIC2_3_LOD_ISO_QUALITY_LOW 0x00000000 +#define GM107_TIC2_3_LOD_ISO_QUALITY_HIGH 0x00040000 +#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER__MASK 0x00180000 +#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER__SHIFT 19 +#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER_NONE 0x00000000 +#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER_CONST_ONE 0x00080000 +#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER_CONST_TWO 0x00100000 +#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER_SQRT 0x00180000 +#define GM107_TIC2_3_ANISO_SPREAD_SCALE__MASK 0x03e00000 +#define GM107_TIC2_3_ANISO_SPREAD_SCALE__SHIFT 21 +#define GM107_TIC2_3_USE_HEADER_OPT_CONTROL 0x04000000 +#define GM107_TIC2_3_DEPTH_TEXTURE 0x08000000 +#define GM107_TIC2_3_MAX_MIP_LEVEL__MASK 0xf0000000 +#define GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT 28 + +#define GM107_TIC2_4 0x00000010 +#define GM107_TIC2_4_WIDTH_MINUS_ONE_BITS_15_TO_0__MASK 0x0000ffff +#define GM107_TIC2_4_WIDTH_MINUS_ONE_BITS_15_TO_0__SHIFT 0 +#define GM107_TIC2_4_WIDTH_MINUS_ONE__MASK 0x0000ffff +#define GM107_TIC2_4_WIDTH_MINUS_ONE__SHIFT 0 +#define GM107_TIC2_4_ANISO_SPREAD_MAX_LOG2__MASK 0x00380000 +#define GM107_TIC2_4_ANISO_SPREAD_MAX_LOG2__SHIFT 19 +#define GM107_TIC2_4_SRGB_CONVERSION 0x00400000 +#define GM107_TIC2_4_TEXTURE_TYPE__MASK 0x07800000 +#define GM107_TIC2_4_TEXTURE_TYPE__SHIFT 23 +#define GM107_TIC2_4_TEXTURE_TYPE_ONE_D 0x00000000 +#define GM107_TIC2_4_TEXTURE_TYPE_TWO_D 0x00800000 +#define GM107_TIC2_4_TEXTURE_TYPE_THREE_D 0x01000000 +#define GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP 0x01800000 +#define GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY 0x02000000 +#define GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY 0x02800000 +#define GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER 0x03000000 +#define GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x03800000 +#define GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY 0x04000000 +#define GM107_TIC2_4_SECTOR_PROMOTION__MASK 0x18000000 +#define GM107_TIC2_4_SECTOR_PROMOTION__SHIFT 27 +#define GM107_TIC2_4_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x08000000 +#define GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x10000000 +#define GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_4 0x18000000 +#define GM107_TIC2_4_BORDER_SIZE__MASK 0xe0000000 +#define GM107_TIC2_4_BORDER_SIZE__SHIFT 29 +#define GM107_TIC2_4_BORDER_SIZE_ONE 0x00000000 +#define GM107_TIC2_4_BORDER_SIZE_TWO 0x20000000 +#define GM107_TIC2_4_BORDER_SIZE_FOUR 0x40000000 +#define GM107_TIC2_4_BORDER_SIZE_EIGHT 0x60000000 +#define GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR 0xe0000000 + +#define GM107_TIC2_5 0x00000014 +#define GM107_TIC2_5_HEIGHT_MINUS_ONE__MASK 0x0000ffff +#define GM107_TIC2_5_HEIGHT_MINUS_ONE__SHIFT 0 +#define GM107_TIC2_5_DEPTH_MINUS_ONE__MASK 0x3fff0000 +#define GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT 16 +#define GM107_TIC2_5_NORMALIZED_COORDS 0x80000000 + +#define GM107_TIC2_6 0x00000018 +#define GM107_TIC2_6_COLOR_KEY_OP 0x00000001 +#define GM107_TIC2_6_TRILIN_OPT__MASK 0x0000003e +#define GM107_TIC2_6_TRILIN_OPT__SHIFT 1 +#define GM107_TIC2_6_MIP_LOD_BIAS__MASK 0x0007ffc0 +#define GM107_TIC2_6_MIP_LOD_BIAS__SHIFT 6 +#define GM107_TIC2_6_MIP_LOD_BIAS__RADIX 0x00000008 +#define GM107_TIC2_6_ANISO_BIAS__MASK 0x00780000 +#define GM107_TIC2_6_ANISO_BIAS__SHIFT 19 +#define GM107_TIC2_6_ANISO_BIAS__RADIX 0x00000004 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC__MASK 0x01800000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC__SHIFT 23 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_HALF 0x00000000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_ONE 0x00800000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO 0x01000000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_MAX 0x01800000 +#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC__MASK 0x06000000 +#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC__SHIFT 25 +#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_HALF 0x00000000 +#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE 0x02000000 +#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_TWO 0x04000000 +#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_MAX 0x06000000 +#define GM107_TIC2_6_MAX_ANISOTROPY__MASK 0x38000000 +#define GM107_TIC2_6_MAX_ANISOTROPY__SHIFT 27 +#define GM107_TIC2_6_MAX_ANISOTROPY_1_TO_1 0x00000000 +#define GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1 0x08000000 +#define GM107_TIC2_6_MAX_ANISOTROPY_4_TO_1 0x10000000 +#define GM107_TIC2_6_MAX_ANISOTROPY_6_TO_1 0x18000000 +#define GM107_TIC2_6_MAX_ANISOTROPY_8_TO_1 0x20000000 +#define GM107_TIC2_6_MAX_ANISOTROPY_10_TO_1 0x28000000 +#define GM107_TIC2_6_MAX_ANISOTROPY_12_TO_1 0x30000000 +#define GM107_TIC2_6_MAX_ANISOTROPY_16_TO_1 0x38000000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER__MASK 0xc0000000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER__SHIFT 30 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_NONE 0x00000000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_ONE 0x40000000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO 0x80000000 +#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_SQRT 0xc0000000 + +#define GM107_TIC2_7 0x0000001c +#define GM107_TIC2_7_COLOR_KEY_VALUE__MASK 0xffffffff +#define GM107_TIC2_7_COLOR_KEY_VALUE__SHIFT 0 +#define GM107_TIC2_7_RES_VIEW_MIN_MIP_LEVEL__MASK 0x0000000f +#define GM107_TIC2_7_RES_VIEW_MIN_MIP_LEVEL__SHIFT 0 +#define GM107_TIC2_7_RES_VIEW_MAX_MIP_LEVEL__MASK 0x000000f0 +#define GM107_TIC2_7_RES_VIEW_MAX_MIP_LEVEL__SHIFT 4 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT__MASK 0x00000f00 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT 8 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_1X1 0x00000000 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X1 0x00000100 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X2 0x00000200 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X2 0x00000300 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X2_D3D 0x00000400 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X1_D3D 0x00000500 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X4 0x00000600 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X2_VC_4 0x00000800 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X2_VC_12 0x00000900 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X2_VC_8 0x00000a00 +#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X2_VC_24 0x00000b00 +#define GM107_TIC2_7_MIN_LOD_CLAMP__MASK 0x00fff000 +#define GM107_TIC2_7_MIN_LOD_CLAMP__SHIFT 12 +#define GM107_TIC2_7_MIN_LOD_CLAMP__RADIX 0x00000008 + + +#endif /* GM107_TEXTURE_XML */ diff --git a/src/hwdefs/nvc0_3d.xml.h b/src/hwdefs/nvc0_3d.xml.h index 3bcaa0f..1be5952 100644 --- a/src/hwdefs/nvc0_3d.xml.h +++ b/src/hwdefs/nvc0_3d.xml.h @@ -1,39 +1,23 @@ -#ifndef _HOME_SKEGGSB_GIT_ENVYTOOLS_RNNDB_NVC0_3D_XML -#define _HOME_SKEGGSB_GIT_ENVYTOOLS_RNNDB_NVC0_3D_XML +#ifndef NVC0_3D_XML +#define NVC0_3D_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng headergen tool in this git repository: -http://0x04.net/cgit/index.cgi/rules-ng-ng -git clone git://0x04.net/rules-ng-ng +http://github.com/envytools/envytools/ +git clone https://github.com/envytools/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/skeggsb/git/envytools/rnndb/nv_objects.xml ( 794 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/copyright.xml ( 6452 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv_m2mf.xml ( 2696 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv_object.xml ( 12672 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nvchipsets.xml ( 3617 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv_defs.xml ( 4437 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv50_defs.xml ( 5468 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nvc0_m2mf.xml ( 2687 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv01_2d.xml ( 32584 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv04_dvd.xml ( 3000 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv03_3d.xml ( 5209 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv04_3d.xml ( 17759 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv_3ddefs.xml ( 16394 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv10_3d.xml ( 18437 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv20_3d.xml ( 21107 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv30-40_3d.xml ( 31987 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv50_2d.xml ( 11113 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv50_3d.xml ( 65233 bytes, from 2011-11-30 05:49:35) -- /home/skeggsb/git/envytools/rnndb/nv50_compute.xml ( 14012 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nv84_crypt.xml ( 2071 bytes, from 2011-11-30 05:49:35) -- /home/skeggsb/git/envytools/rnndb/nv31_mpeg.xml ( 2269 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/nvc0_3d.xml ( 52547 bytes, from 2011-11-30 05:49:35) -- /home/skeggsb/git/envytools/rnndb/nvc0_compute.xml ( 10865 bytes, from 2011-10-22 08:01:09) -- /home/skeggsb/git/envytools/rnndb/blob_nvc0_pcopy.xml ( 4516 bytes, from 2011-10-22 08:01:09) - -Copyright (C) 2006-2011 by the following authors: +- rnndb/graph/gf100_3d.xml ( 59971 bytes, from 2014-09-26 00:01:33) +- rnndb/copyright.xml ( 6456 bytes, from 2014-12-31 02:13:31) +- rnndb/nv_defs.xml ( 4399 bytes, from 2013-09-07 03:32:45) +- rnndb/graph/nv_3ddefs.xml ( 16390 bytes, from 2014-09-25 06:32:11) +- rnndb/fifo/nv_object.xml ( 15326 bytes, from 2014-09-25 06:32:11) +- rnndb/nvchipsets.xml ( 2759 bytes, from 2014-10-05 01:51:02) +- rnndb/g80_defs.xml ( 18175 bytes, from 2014-09-25 06:32:11) +- rnndb/graph/gk104_p2mf.xml ( 2376 bytes, from 2014-09-25 06:32:11) + +Copyright (C) 2006-2014 by the following authors: - Artur Huillet <arthur.huillet at free.fr> (ahuillet) - Ben Skeggs (darktama, darktama_) - B. R. <koala_br at users.sourceforge.net> (koala_br) @@ -45,7 +29,7 @@ Copyright (C) 2006-2011 by the following authors: - EdB <edb_ at users.sf.net> (edb_) - Erik Waling <erikwailing at users.sf.net> (erikwaling) - Francisco Jerez <currojerez at riseup.net> (curro) -- imirkin <imirkin at users.sf.net> (imirkin) +- Ilia Mirkin <imirkin at alum.mit.edu> (imirkin) - jb17bsome <jb17bsome at bellsouth.net> (jb17bsome) - Jeremy Kolb <kjeremy at users.sf.net> (kjeremy) - Laurent Carlier <lordheavym at gmail.com> (lordheavy) @@ -93,6 +77,60 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +#define NVE4_3D_UNK0144 0x00000144 + +#define NVE4_3D_UPLOAD 0x00000000 + +#define NVE4_3D_UPLOAD_LINE_LENGTH_IN 0x00000180 + +#define NVE4_3D_UPLOAD_LINE_COUNT 0x00000184 + +#define NVE4_3D_UPLOAD_DST_ADDRESS_HIGH 0x00000188 + +#define NVE4_3D_UPLOAD_DST_ADDRESS_LOW 0x0000018c + +#define NVE4_3D_UPLOAD_DST_PITCH 0x00000190 + +#define NVE4_3D_UPLOAD_DST_TILE_MODE 0x00000194 + +#define NVE4_3D_UPLOAD_DST_WIDTH 0x00000198 + +#define NVE4_3D_UPLOAD_DST_HEIGHT 0x0000019c + +#define NVE4_3D_UPLOAD_DST_DEPTH 0x000001a0 + +#define NVE4_3D_UPLOAD_DST_Z 0x000001a4 + +#define NVE4_3D_UPLOAD_DST_X 0x000001a8 + +#define NVE4_3D_UPLOAD_DST_Y 0x000001ac + +#define NVE4_3D_UPLOAD_EXEC 0x000001b0 +#define NVE4_3D_UPLOAD_EXEC_LINEAR 0x00000001 +#define NVE4_3D_UPLOAD_EXEC_UNK1__MASK 0x0000007e +#define NVE4_3D_UPLOAD_EXEC_UNK1__SHIFT 1 +#define NVE4_3D_UPLOAD_EXEC_BUF_NOTIFY 0x00000300 +#define NVE4_3D_UPLOAD_EXEC_UNK12__MASK 0x0000f000 +#define NVE4_3D_UPLOAD_EXEC_UNK12__SHIFT 12 + +#define NVE4_3D_UPLOAD_DATA 0x000001b4 + +#define NVE4_3D_UPLOAD_QUERY_ADDRESS_HIGH 0x000001dc + +#define NVE4_3D_UPLOAD_QUERY_ADDRESS_LOW 0x000001e0 + +#define NVE4_3D_UPLOAD_QUERY_SEQUENCE 0x000001e4 + +#define NVE4_3D_UPLOAD_UNK01F0 0x000001f0 + +#define NVE4_3D_UPLOAD_UNK01F4 0x000001f4 + +#define NVE4_3D_UPLOAD_UNK01F8 0x000001f8 + +#define NVE4_3D_UPLOAD_UNK01FC 0x000001fc + #define NVC0_3D_UNK200 0x00000200 #define NVC0_3D_UNK204 0x00000204 @@ -101,7 +139,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_LINE_WIDTH_SEPARATE 0x0000020c -#define NVC0_3D_EARLY_FRAGMENT_TESTS 0x00000210 +#define NVC0_3D_FORCE_EARLY_FRAGMENT_TESTS 0x00000210 #define NVC0_3D_UNK214 0x00000214 @@ -119,91 +157,110 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_UNK0220__ESIZE 0x00000004 #define NVC0_3D_UNK0220__LEN 0x00000028 -#define NVC0_3D_UNK02C0 0x000002c0 +#define NVC0_3D_UNK02C0 0x000002c0 -#define NVC0_3D_UNK02C4 0x000002c4 +#define NVC0_3D_UNK02C4 0x000002c4 #define NVC0_3D_GLOBAL_BASE 0x000002c8 #define NVC0_3D_GLOBAL_BASE_HIGH__MASK 0x000000ff -#define NVC0_3D_GLOBAL_BASE_HIGH__SHIFT 0 -#define NVC0_3D_GLOBAL_BASE_INDEX__MASK 0x00ff0000 +#define NVC0_3D_GLOBAL_BASE_HIGH__SHIFT 0 +#define NVC0_3D_GLOBAL_BASE_INDEX__MASK 0x00ff0000 #define NVC0_3D_GLOBAL_BASE_INDEX__SHIFT 16 #define NVC0_3D_GLOBAL_BASE_READ_OK 0x40000000 #define NVC0_3D_GLOBAL_BASE_WRITE_OK 0x80000000 -#define NVC0_3D_UNK02CC 0x000002cc +#define NVC0_3D_UNK02CC 0x000002cc + +#define NVC0_3D_UNK02D0 0x000002d0 -#define NVC0_3D_UNK02D0 0x000002d0 +#define NVC0_3D_UNK02D4 0x000002d4 -#define NVC0_3D_UNK02D4 0x000002d4 +#define NVC0_3D_UNK02D8 0x000002d8 -#define NVC0_3D_UNK02D8 0x000002d8 +#define NVC8_3D_UNK02E0 0x000002e0 -#define NVC1_3D_UNK02E4 0x000002e4 +#define NVC1_3D_UNK02E4 0x000002e4 #define NVC1_3D_UNK02E4_UNK0 0x00000001 #define NVC1_3D_UNK02E4_UNK4 0x00000010 #define NVC1_3D_UNK02E4_UNK8 0x00000100 #define NVC1_3D_UNK02E4_UNK12__MASK 0x0000f000 #define NVC1_3D_UNK02E4_UNK12__SHIFT 12 -#define NVC0_3D_UNK02EC 0x000002ec +#define NVC8_3D_UNK02E8 0x000002e8 + +#define NVC0_3D_UNK02EC 0x000002ec #define NVC0_3D_UNK02EC_UNK0 0x00000001 #define NVC0_3D_UNK02EC_UNK4__MASK 0x00000ff0 #define NVC0_3D_UNK02EC_UNK4__SHIFT 4 -#define NVC0_3D_UNK0300 0x00000300 +#define NVC8_3D_UNK02F8 0x000002f8 + +#define NVC8_3D_UNK02FC 0x000002fc -#define NVC0_3D_UNK0304 0x00000304 +#define NVC0_3D_UNK0300 0x00000300 + +#define NVC0_3D_UNK0304 0x00000304 #define NVC0_3D_CACHE_SPLIT 0x00000308 #define NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1 0x00000001 +#define NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1 0x00000002 #define NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1 0x00000003 -#define NVC0_3D_UNK030C 0x0000030c +#define NVC0_3D_UNK030C 0x0000030c + +#define NVC0_3D_UNK0310 0x00000310 -#define NVC0_3D_UNK0310 0x00000310 +#define NVE4_3D_UNK0310 0x00000310 -#define NVC0_3D_UNK0314 0x00000314 +#define NVC0_3D_UNK0314 0x00000314 -#define NVC0_3D_UNK0318 0x00000318 +#define NVC0_3D_UNK0318 0x00000318 -#define NVC0_3D_UNK031C 0x0000031c +#define NVC0_3D_UNK031C 0x0000031c #define NVC0_3D_TESS_MODE 0x00000320 #define NVC0_3D_TESS_MODE_PRIM__MASK 0x00000003 #define NVC0_3D_TESS_MODE_PRIM__SHIFT 0 -#define NVC0_3D_TESS_MODE_PRIM_ISOLINES 0x00000000 +#define NVC0_3D_TESS_MODE_PRIM_ISOLINES 0x00000000 #define NVC0_3D_TESS_MODE_PRIM_TRIANGLES 0x00000001 #define NVC0_3D_TESS_MODE_PRIM_QUADS 0x00000002 -#define NVC0_3D_TESS_MODE_SPACING__MASK 0x00000030 +#define NVC0_3D_TESS_MODE_SPACING__MASK 0x00000030 #define NVC0_3D_TESS_MODE_SPACING__SHIFT 4 -#define NVC0_3D_TESS_MODE_SPACING_EQUAL 0x00000000 +#define NVC0_3D_TESS_MODE_SPACING_EQUAL 0x00000000 #define NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD 0x00000010 #define NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN 0x00000020 #define NVC0_3D_TESS_MODE_CW 0x00000100 #define NVC0_3D_TESS_MODE_CONNECTED 0x00000200 #define NVC0_3D_TESS_LEVEL_OUTER(i0) (0x00000324 + 0x4*(i0)) -#define NVC0_3D_TESS_LEVEL_OUTER__ESIZE 0x00000004 +#define NVC0_3D_TESS_LEVEL_OUTER__ESIZE 0x00000004 #define NVC0_3D_TESS_LEVEL_OUTER__LEN 0x00000004 #define NVC0_3D_TESS_LEVEL_INNER(i0) (0x00000334 + 0x4*(i0)) -#define NVC0_3D_TESS_LEVEL_INNER__ESIZE 0x00000004 +#define NVC0_3D_TESS_LEVEL_INNER__ESIZE 0x00000004 #define NVC0_3D_TESS_LEVEL_INNER__LEN 0x00000002 #define NVC0_3D_UNK033C(i0) (0x0000033c + 0x4*(i0)) #define NVC0_3D_UNK033C__ESIZE 0x00000004 #define NVC0_3D_UNK033C__LEN 0x00000009 -#define NVC0_3D_UNK0360 0x00000360 +#define NVC0_3D_UNK0360 0x00000360 + +#define NVC0_3D_UNK0364 0x00000364 -#define NVC0_3D_UNK0364 0x00000364 +#define NVC0_3D_UNK0368 0x00000368 -#define NVC0_3D_UNK0368 0x00000368 +#define NVC8_3D_UNK036C 0x0000036c + +#define NVC8_3D_UNK0370 0x00000370 + +#define NVC8_3D_UNK0374 0x00000374 + +#define NVC8_3D_UNK0378 0x00000378 #define NVC0_3D_RASTERIZE_ENABLE 0x0000037c -#define NVC0_3D_TFB(i0) (0x00000380 + 0x20*(i0)) +#define NVC0_3D_TFB(i0) (0x00000380 + 0x20*(i0)) #define NVC0_3D_TFB__ESIZE 0x00000020 #define NVC0_3D_TFB__LEN 0x00000004 @@ -223,7 +280,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_TFB_STREAM(i0) (0x00000700 + 0x10*(i0)) #define NVC0_3D_TFB_STREAM__ESIZE 0x00000010 -#define NVC0_3D_TFB_STREAM__LEN 0x00000004 +#define NVC0_3D_TFB_STREAM__LEN 0x00000004 #define NVC0_3D_TFB_VARYING_COUNT(i0) (0x00000704 + 0x10*(i0)) #define NVC0_3D_TFB_VARYING_COUNT__ESIZE 0x00000010 @@ -233,22 +290,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_TFB_BUFFER_STRIDE__ESIZE 0x00000010 #define NVC0_3D_TFB_BUFFER_STRIDE__LEN 0x00000004 -#define NVC0_3D_UNK0740 0x00000740 +#define NVC0_3D_UNK0740 0x00000740 #define NVC0_3D_TFB_ENABLE 0x00000744 -#define NVC0_3D_UNK0748 0x00000748 +#define NVC0_3D_UNK0748 0x00000748 -#define NVC0_3D_UNK074C 0x0000074c +#define NVC0_3D_UNK074C 0x0000074c -#define NVC0_3D_UNK0750 0x00000750 +#define NVC0_3D_UNK0750 0x00000750 #define NVC0_3D_SAMPLE_SHADING 0x00000754 #define NVC0_3D_SAMPLE_SHADING_MIN_SAMPLES__MASK 0x0000000f #define NVC0_3D_SAMPLE_SHADING_MIN_SAMPLES__SHIFT 0 #define NVC0_3D_SAMPLE_SHADING_ENABLE 0x00000010 -#define NVC0_3D_UNK075C 0x0000075c +#define NVC0_3D_UNK075C 0x0000075c #define NVC0_3D_UNK0760(i0) (0x00000760 + 0x4*(i0)) #define NVC0_3D_UNK0760__ESIZE 0x00000004 @@ -280,7 +337,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_TEMP_SIZE_LOW 0x0000079c -#define NVC0_3D_WARP_TEMP_ALLOC 0x000007a0 +#define NVC0_3D_WARP_TEMP_ALLOC 0x000007a0 + +#define NVC8_3D_UNK07A4(i0) (0x000007a4 + 0x4*(i0)) +#define NVC8_3D_UNK07A4__ESIZE 0x00000004 +#define NVC8_3D_UNK07A4__LEN 0x00000002 + +#define NVE4_3D_UNK07AC 0x000007ac #define NVC0_3D_UNK07B0(i0) (0x000007b0 + 0x4*(i0)) #define NVC0_3D_UNK07B0__ESIZE 0x00000004 @@ -306,11 +369,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_UNK07D0_UNK28__MASK 0xf0000000 #define NVC0_3D_UNK07D0_UNK28__SHIFT 28 -#define NVC0_3D_UNK07DC 0x000007dc +#define NVC0_3D_UNK07DC 0x000007dc -#define NVC0_3D_UNK07E0 0x000007e0 +#define NVC0_3D_UNK07E0 0x000007e0 -#define NVC0_3D_UNK07E4 0x000007e4 +#define NVC0_3D_UNK07E4 0x000007e4 #define NVC0_3D_ZCULL_ADDRESS_HIGH 0x000007e8 @@ -318,15 +381,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_ZCULL_LIMIT_HIGH 0x000007f0 -#define NVC0_3D_ZCULL_LIMIT_LOW 0x000007f4 +#define NVC0_3D_ZCULL_LIMIT_LOW 0x000007f4 -#define NVC0_3D_UNK07F8 0x000007f8 +#define NVC0_3D_UNK07F8 0x000007f8 #define NVC0_3D_UNK07F8_UNK0 0x00000001 #define NVC0_3D_UNK07F8_UNK1 0x00000010 +#define NVE4_3D_UNK07FC 0x000007fc + #define NVC0_3D_RT(i0) (0x00000800 + 0x40*(i0)) #define NVC0_3D_RT__ESIZE 0x00000040 -#define NVC0_3D_RT__LEN 0x00000008 +#define NVC0_3D_RT__LEN 0x00000008 #define NVC0_3D_RT_ADDRESS_HIGH(i0) (0x00000800 + 0x40*(i0)) @@ -359,15 +424,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_RT_UNK14(i0) (0x00000824 + 0x40*(i0)) #define NVC0_3D_VIEWPORT_SCALE_X(i0) (0x00000a00 + 0x20*(i0)) -#define NVC0_3D_VIEWPORT_SCALE_X__ESIZE 0x00000020 +#define NVC0_3D_VIEWPORT_SCALE_X__ESIZE 0x00000020 #define NVC0_3D_VIEWPORT_SCALE_X__LEN 0x00000010 #define NVC0_3D_VIEWPORT_SCALE_Y(i0) (0x00000a04 + 0x20*(i0)) -#define NVC0_3D_VIEWPORT_SCALE_Y__ESIZE 0x00000020 +#define NVC0_3D_VIEWPORT_SCALE_Y__ESIZE 0x00000020 #define NVC0_3D_VIEWPORT_SCALE_Y__LEN 0x00000010 #define NVC0_3D_VIEWPORT_SCALE_Z(i0) (0x00000a08 + 0x20*(i0)) -#define NVC0_3D_VIEWPORT_SCALE_Z__ESIZE 0x00000020 +#define NVC0_3D_VIEWPORT_SCALE_Z__ESIZE 0x00000020 #define NVC0_3D_VIEWPORT_SCALE_Z__LEN 0x00000010 #define NVC0_3D_VIEWPORT_TRANSLATE_X(i0) (0x00000a0c + 0x20*(i0)) @@ -386,9 +451,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VIEWPORT_HORIZ__ESIZE 0x00000010 #define NVC0_3D_VIEWPORT_HORIZ__LEN 0x00000010 #define NVC0_3D_VIEWPORT_HORIZ_X__MASK 0x0000ffff -#define NVC0_3D_VIEWPORT_HORIZ_X__SHIFT 0 +#define NVC0_3D_VIEWPORT_HORIZ_X__SHIFT 0 #define NVC0_3D_VIEWPORT_HORIZ_W__MASK 0xffff0000 -#define NVC0_3D_VIEWPORT_HORIZ_W__SHIFT 16 +#define NVC0_3D_VIEWPORT_HORIZ_W__SHIFT 16 #define NVC0_3D_VIEWPORT_VERT(i0) (0x00000c04 + 0x10*(i0)) #define NVC0_3D_VIEWPORT_VERT__ESIZE 0x00000010 @@ -399,7 +464,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VIEWPORT_VERT_H__SHIFT 16 #define NVC0_3D_DEPTH_RANGE_NEAR(i0) (0x00000c08 + 0x10*(i0)) -#define NVC0_3D_DEPTH_RANGE_NEAR__ESIZE 0x00000010 +#define NVC0_3D_DEPTH_RANGE_NEAR__ESIZE 0x00000010 #define NVC0_3D_DEPTH_RANGE_NEAR__LEN 0x00000010 #define NVC0_3D_DEPTH_RANGE_FAR(i0) (0x00000c0c + 0x10*(i0)) @@ -422,7 +487,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CLIP_RECT_VERT_MAX__MASK 0xffff0000 #define NVC0_3D_CLIP_RECT_VERT_MAX__SHIFT 16 -#define NVC0_3D_CLIPID_REGION_HORIZ(i0) (0x00000d40 + 0x8*(i0)) +#define NVC0_3D_CLIPID_REGION_HORIZ(i0) (0x00000d40 + 0x8*(i0)) #define NVC0_3D_CLIPID_REGION_HORIZ__ESIZE 0x00000008 #define NVC0_3D_CLIPID_REGION_HORIZ__LEN 0x00000004 #define NVC0_3D_CLIPID_REGION_HORIZ_X__MASK 0x0000ffff @@ -432,13 +497,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CLIPID_REGION_VERT(i0) (0x00000d44 + 0x8*(i0)) #define NVC0_3D_CLIPID_REGION_VERT__ESIZE 0x00000008 -#define NVC0_3D_CLIPID_REGION_VERT__LEN 0x00000004 +#define NVC0_3D_CLIPID_REGION_VERT__LEN 0x00000004 #define NVC0_3D_CLIPID_REGION_VERT_Y__MASK 0x0000ffff #define NVC0_3D_CLIPID_REGION_VERT_Y__SHIFT 0 #define NVC0_3D_CLIPID_REGION_VERT_H__MASK 0xffff0000 #define NVC0_3D_CLIPID_REGION_VERT_H__SHIFT 16 -#define NVC0_3D_UNK0D60 0x00000d60 +#define NVC0_3D_UNK0D60 0x00000d60 #define NVC0_3D_CALL_LIMIT_LOG 0x00000d64 @@ -463,32 +528,49 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_UNK0D6C(i0) (0x00000d6c + 0x4*(i0)) #define NVC0_3D_UNK0D6C__ESIZE 0x00000004 #define NVC0_3D_UNK0D6C__LEN 0x00000002 -#define NVC0_3D_UNK0D6C_X__MASK 0x0000ffff +#define NVC0_3D_UNK0D6C_X__MASK 0x0000ffff #define NVC0_3D_UNK0D6C_X__SHIFT 0 -#define NVC0_3D_UNK0D6C_Y__MASK 0xffff0000 +#define NVC0_3D_UNK0D6C_Y__MASK 0xffff0000 #define NVC0_3D_UNK0D6C_Y__SHIFT 16 #define NVC0_3D_VERTEX_BUFFER_FIRST 0x00000d74 #define NVC0_3D_VERTEX_BUFFER_COUNT 0x00000d78 -#define NVC0_3D_UNK0D7C 0x00000d7c +#define NVC0_3D_DEPTH_CLIP_NEGATIVE_Z 0x00000d7c -#define NVC0_3D_CLEAR_COLOR(i0) (0x00000d80 + 0x4*(i0)) +#define NVC0_3D_CLEAR_COLOR(i0) (0x00000d80 + 0x4*(i0)) #define NVC0_3D_CLEAR_COLOR__ESIZE 0x00000004 #define NVC0_3D_CLEAR_COLOR__LEN 0x00000004 #define NVC0_3D_CLEAR_DEPTH 0x00000d90 -#define NVC0_3D_UNK0D94 0x00000d94 +#define NVC0_3D_UNK0D94 0x00000d94 -#define NVC0_3D_UNK0D9C 0x00000d9c +#define NVE4_3D_UNK0D98 0x00000d98 + +#define NVC0_3D_UNK0D9C 0x00000d9c #define NVC0_3D_CLEAR_STENCIL 0x00000da0 +#define NVE4_3D_UNK0DA4 0x00000da4 +#define NVE4_3D_UNK0DA4_UNK0 0x00000001 +#define NVE4_3D_UNK0DA4_UNK4 0x00000010 +#define NVE4_3D_UNK0DA4_UNK12 0x00001000 + +#define NVC0_3D_POLYGON_MODE_FRONT 0x00000dac +#define NVC0_3D_POLYGON_MODE_FRONT_POINT 0x00001b00 +#define NVC0_3D_POLYGON_MODE_FRONT_LINE 0x00001b01 +#define NVC0_3D_POLYGON_MODE_FRONT_FILL 0x00001b02 + +#define NVC0_3D_POLYGON_MODE_BACK 0x00000db0 +#define NVC0_3D_POLYGON_MODE_BACK_POINT 0x00001b00 +#define NVC0_3D_POLYGON_MODE_BACK_LINE 0x00001b01 +#define NVC0_3D_POLYGON_MODE_BACK_FILL 0x00001b02 + #define NVC0_3D_POLYGON_SMOOTH_ENABLE 0x00000db4 -#define NVC0_3D_UNK0DB8 0x00000db8 +#define NVC0_3D_UNK0DB8 0x00000db8 #define NVC0_3D_ZCULL_UNK0DBC 0x00000dbc #define NVC0_3D_ZCULL_UNK0DBC_UNK0 0x00000001 @@ -511,19 +593,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_ZCULL_UNK0DD8_UNK16__MASK 0xffff0000 #define NVC0_3D_ZCULL_UNK0DD8_UNK16__SHIFT 16 -#define NVC0_3D_UNK0DDC 0x00000ddc +#define NVC0_3D_UNK0DDC 0x00000ddc #define NVC0_3D_WATCHDOG_TIMER 0x00000de4 -#define NVC0_3D_UNK0DE8 0x00000de8 +#define NVC0_3D_PRIM_RESTART_WITH_DRAW_ARRAYS 0x00000de8 -#define NVC0_3D_UNK0DEC 0x00000dec +#define NVC0_3D_UNK0DEC 0x00000dec -#define NVC0_3D_UNK0DF4 0x00000df4 +#define NVC0_3D_UNK0DF4 0x00000df4 -#define NVC0_3D_WINDOW_OFFSET_X 0x00000df8 +#define NVC0_3D_WINDOW_OFFSET_X 0x00000df8 -#define NVC0_3D_WINDOW_OFFSET_Y 0x00000dfc +#define NVC0_3D_WINDOW_OFFSET_Y 0x00000dfc #define NVC0_3D_SCISSOR_ENABLE(i0) (0x00000e00 + 0x10*(i0)) #define NVC0_3D_SCISSOR_ENABLE__ESIZE 0x00000010 @@ -532,23 +614,27 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_SCISSOR_HORIZ(i0) (0x00000e04 + 0x10*(i0)) #define NVC0_3D_SCISSOR_HORIZ__ESIZE 0x00000010 #define NVC0_3D_SCISSOR_HORIZ__LEN 0x00000010 -#define NVC0_3D_SCISSOR_HORIZ_MIN__MASK 0x0000ffff +#define NVC0_3D_SCISSOR_HORIZ_MIN__MASK 0x0000ffff #define NVC0_3D_SCISSOR_HORIZ_MIN__SHIFT 0 -#define NVC0_3D_SCISSOR_HORIZ_MAX__MASK 0xffff0000 +#define NVC0_3D_SCISSOR_HORIZ_MAX__MASK 0xffff0000 #define NVC0_3D_SCISSOR_HORIZ_MAX__SHIFT 16 #define NVC0_3D_SCISSOR_VERT(i0) (0x00000e08 + 0x10*(i0)) #define NVC0_3D_SCISSOR_VERT__ESIZE 0x00000010 #define NVC0_3D_SCISSOR_VERT__LEN 0x00000010 #define NVC0_3D_SCISSOR_VERT_MIN__MASK 0x0000ffff -#define NVC0_3D_SCISSOR_VERT_MIN__SHIFT 0 +#define NVC0_3D_SCISSOR_VERT_MIN__SHIFT 0 #define NVC0_3D_SCISSOR_VERT_MAX__MASK 0xffff0000 -#define NVC0_3D_SCISSOR_VERT_MAX__SHIFT 16 +#define NVC0_3D_SCISSOR_VERT_MAX__SHIFT 16 #define NVC0_3D_UNK0F00(i0) (0x00000f00 + 0x4*(i0)) #define NVC0_3D_UNK0F00__ESIZE 0x00000004 #define NVC0_3D_UNK0F00__LEN 0x00000004 +#define NVE4_3D_UNK0F20(i0) (0x00000f20 + 0x4*(i0)) +#define NVE4_3D_UNK0F20__ESIZE 0x00000004 +#define NVE4_3D_UNK0F20__LEN 0x00000005 + #define NVC0_3D_STENCIL_BACK_FUNC_REF 0x00000f54 #define NVC0_3D_STENCIL_BACK_MASK 0x00000f58 @@ -559,11 +645,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VERTEX_RUNOUT_ADDRESS_LOW 0x00000f88 -#define NVC0_3D_UNK0F8C 0x00000f8c +#define NVC0_3D_UNK0F8C 0x00000f8c #define NVC0_3D_COLOR_MASK_COMMON 0x00000f90 -#define NVC0_3D_UNK0F98 0x00000f98 +#define NVC0_3D_UNK0F98 0x00000f98 #define NVC0_3D_DEPTH_BOUNDS(i0) (0x00000f9c + 0x4*(i0)) #define NVC0_3D_DEPTH_BOUNDS__ESIZE 0x00000004 @@ -571,7 +657,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_RT_SEPARATE_FRAG_DATA 0x00000fac -#define NVC0_3D_UNK0FB0 0x00000fb0 +#define NVC0_3D_UNK0FB0 0x00000fb0 #define NVC0_3D_MSAA_MASK(i0) (0x00000fbc + 0x4*(i0)) #define NVC0_3D_MSAA_MASK__ESIZE 0x00000004 @@ -581,7 +667,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CLIPID_ADDRESS_LOW 0x00000fd0 -#define NVC0_3D_UNK0FDC 0x00000fdc +#define NVC0_3D_UNK0FDC 0x00000fdc #define NVC0_3D_ZETA_ADDRESS_HIGH 0x00000fe0 @@ -605,59 +691,63 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_SCREEN_SCISSOR_VERT_Y__MASK 0x0000ffff #define NVC0_3D_SCREEN_SCISSOR_VERT_Y__SHIFT 0 -#define NVC0_3D_UNK1000 0x00001000 +#define NVC0_3D_UNK1000 0x00001000 -#define NVC0_3D_UNK1008 0x00001008 +#define NVC0_3D_UNK1008 0x00001008 -#define NVC0_3D_UNK100C 0x0000100c +#define NVC0_3D_UNK100C 0x0000100c -#define NVC0_3D_UNK1010 0x00001010 +#define NVC0_3D_UNK1010 0x00001010 -#define NVC0_3D_UNK1018 0x00001018 +#define NVC0_3D_UNK1018 0x00001018 -#define NVC0_3D_UNK101C 0x0000101c +#define NVC0_3D_UNK101C 0x0000101c -#define NVC0_3D_UNK1020 0x00001020 +#define NVC0_3D_UNK1020 0x00001020 -#define NVC0_3D_UNK1024 0x00001024 +#define NVC0_3D_UNK1024 0x00001024 -#define NVC0_3D_UNK10CC 0x000010cc +#define NVC0_3D_UNK1040(i0) (0x00001040 + 0x4*(i0)) +#define NVC0_3D_UNK1040__ESIZE 0x00000004 +#define NVC0_3D_UNK1040__LEN 0x00000010 + +#define NVC0_3D_UNK10CC 0x000010cc #define NVC0_3D_UNK10CC_UNK0__MASK 0x000000ff #define NVC0_3D_UNK10CC_UNK0__SHIFT 0 #define NVC0_3D_UNK10CC_UNK16__MASK 0x00ff0000 #define NVC0_3D_UNK10CC_UNK16__SHIFT 16 -#define NVC0_3D_UNK10E0 0x000010e0 +#define NVC0_3D_UNK10E0 0x000010e0 #define NVC0_3D_UNK10E0_UNK0__MASK 0x000000ff #define NVC0_3D_UNK10E0_UNK0__SHIFT 0 #define NVC0_3D_UNK10E0_UNK16__MASK 0x00ff0000 #define NVC0_3D_UNK10E0_UNK16__SHIFT 16 -#define NVC0_3D_UNK10E4 0x000010e4 +#define NVC0_3D_UNK10E4 0x000010e4 #define NVC0_3D_UNK10E4_UNK0__MASK 0x000000ff #define NVC0_3D_UNK10E4_UNK0__SHIFT 0 #define NVC0_3D_UNK10E4_UNK16__MASK 0x00ff0000 #define NVC0_3D_UNK10E4_UNK16__SHIFT 16 -#define NVC0_3D_UNK10E8 0x000010e8 +#define NVC0_3D_UNK10E8 0x000010e8 #define NVC0_3D_UNK10E8_UNK0__MASK 0x0000003f #define NVC0_3D_UNK10E8_UNK0__SHIFT 0 #define NVC0_3D_UNK10E8_UNK16__MASK 0x003f0000 #define NVC0_3D_UNK10E8_UNK16__SHIFT 16 -#define NVC0_3D_UNK10EC 0x000010ec +#define NVC0_3D_UNK10EC 0x000010ec #define NVC0_3D_UNK10EC_UNK0__MASK 0x000000ff #define NVC0_3D_UNK10EC_UNK0__SHIFT 0 #define NVC0_3D_UNK10EC_UNK16__MASK 0x00ff0000 #define NVC0_3D_UNK10EC_UNK16__SHIFT 16 -#define NVC0_3D_UNK10F0 0x000010f0 +#define NVC0_3D_UNK10F0 0x000010f0 #define NVC0_3D_UNK10F0_UNK0__MASK 0x000000ff #define NVC0_3D_UNK10F0_UNK0__SHIFT 0 #define NVC0_3D_UNK10F0_UNK16__MASK 0x00ff0000 #define NVC0_3D_UNK10F0_UNK16__SHIFT 16 -#define NVC0_3D_UNK10F4 0x000010f4 +#define NVC0_3D_UNK10F4 0x000010f4 #define NVC0_3D_UNK10F4_UNK0 0x00000001 #define NVC0_3D_UNK10F4_UNK4 0x00000010 #define NVC0_3D_UNK10F4_UNK8 0x00000100 @@ -668,11 +758,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CLEAR_FLAGS_SCISSOR 0x00000100 #define NVC0_3D_CLEAR_FLAGS_VIEWPORT 0x00001000 -#define NVC0_3D_UNK10FC 0x000010fc +#define NVC0_3D_UNK10FC 0x000010fc -#define NVC0_3D_UNK110C 0x0000110c +#define NVC0_3D_UNK110C 0x0000110c -#define NVC0_3D_UNK1110 0x00001110 +#define NVC0_3D_UNK1110 0x00001110 #define NVC0_3D_WRCACHE_FLUSH 0x00001114 @@ -682,11 +772,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VTX_ATTR_MASK_UNK0DD0_ALT__ESIZE 0x00000004 #define NVC0_3D_VTX_ATTR_MASK_UNK0DD0_ALT__LEN 0x00000004 -#define NVC0_3D_UNK1140 0x00001140 +#define NVC0_3D_UNK1140 0x00001140 -#define NVC0_3D_UNK1144 0x00001144 +#define NVC0_3D_UNK1144 0x00001144 -#define NVC0_3D_VTX_ATTR_DEFINE 0x0000114c +#define NVC0_3D_VTX_ATTR_DEFINE 0x0000114c #define NVC0_3D_VTX_ATTR_DEFINE_ATTR__MASK 0x000000ff #define NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT 0 #define NVC0_3D_VTX_ATTR_DEFINE_COMP__MASK 0x00000700 @@ -696,8 +786,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VTX_ATTR_DEFINE_SIZE__MASK 0x00007000 #define NVC0_3D_VTX_ATTR_DEFINE_SIZE__SHIFT 12 #define NVC0_3D_VTX_ATTR_DEFINE_SIZE_8 0x00001000 -#define NVC0_3D_VTX_ATTR_DEFINE_SIZE_16 0x00002000 -#define NVC0_3D_VTX_ATTR_DEFINE_SIZE_32 0x00004000 +#define NVC0_3D_VTX_ATTR_DEFINE_SIZE_16 0x00002000 +#define NVC0_3D_VTX_ATTR_DEFINE_SIZE_32 0x00004000 #define NVC0_3D_VTX_ATTR_DEFINE_TYPE__MASK 0x00070000 #define NVC0_3D_VTX_ATTR_DEFINE_TYPE__SHIFT 16 #define NVC0_3D_VTX_ATTR_DEFINE_TYPE_SNORM 0x00010000 @@ -720,39 +810,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST 0x00000040 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__MASK 0x001fff80 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT 7 -#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE__MASK 0x07e00000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE__MASK 0x07e00000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE__SHIFT 21 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32_32_32 0x00200000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32_32 0x00400000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_16_16_16_16 0x00600000 -#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32 0x00800000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32 0x00800000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_16_16_16 0x00a00000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_8_8_8_8 0x01400000 -#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_16_16 0x01e00000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_16_16 0x01e00000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 0x02400000 -#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_8_8_8 0x02600000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_8_8_8 0x02600000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_8_8 0x03000000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_16 0x03600000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_8 0x03a00000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_10_10_10_2 0x06000000 -#define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE__MASK 0x38000000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_11_11_10 0x06200000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE__MASK 0x38000000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE__SHIFT 27 -#define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_SNORM 0x08000000 -#define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_UNORM 0x10000000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_SNORM 0x08000000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_UNORM 0x10000000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_SINT 0x18000000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_UINT 0x20000000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_USCALED 0x28000000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_SSCALED 0x30000000 -#define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT 0x38000000 +#define NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT 0x38000000 #define NVC0_3D_VERTEX_ATTRIB_FORMAT_BGRA 0x80000000 -#define NVC0_3D_UNK1214 0x00001214 +#define NVC0_3D_UNK1214 0x00001214 -#define NVC0_3D_UNK1218 0x00001218 +#define NVC0_3D_UNK1218 0x00001218 #define NVC0_3D_RT_CONTROL 0x0000121c #define NVC0_3D_RT_CONTROL_COUNT__MASK 0x0000000f -#define NVC0_3D_RT_CONTROL_COUNT__SHIFT 0 +#define NVC0_3D_RT_CONTROL_COUNT__SHIFT 0 #define NVC0_3D_RT_CONTROL_MAP0__MASK 0x00000070 #define NVC0_3D_RT_CONTROL_MAP0__SHIFT 4 #define NVC0_3D_RT_CONTROL_MAP1__MASK 0x00000380 @@ -770,13 +861,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_RT_CONTROL_MAP7__MASK 0x0e000000 #define NVC0_3D_RT_CONTROL_MAP7__SHIFT 25 -#define NVC0_3D_UNK1220 0x00001220 +#define NVC0_3D_UNK1220 0x00001220 #define NVC0_3D_ZETA_HORIZ 0x00001228 #define NVC0_3D_ZETA_VERT 0x0000122c -#define NVC0_3D_ZETA_ARRAY_MODE 0x00001230 +#define NVC0_3D_ZETA_ARRAY_MODE 0x00001230 #define NVC0_3D_ZETA_ARRAY_MODE_LAYERS__MASK 0x0000ffff #define NVC0_3D_ZETA_ARRAY_MODE_LAYERS__SHIFT 0 #define NVC0_3D_ZETA_ARRAY_MODE_UNK 0x00010000 @@ -785,23 +876,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_DRAW_TFB_BYTES 0x0000123c -#define NVC0_3D_UNK1284 0x00001284 +#define NVC0_3D_UNK1284 0x00001284 #define NVC0_3D_UNK1288_TIC_FLUSH 0x00001288 -#define NVC0_3D_UNK1290 0x00001290 +#define NVC0_3D_UNK1290 0x00001290 -#define NVC0_3D_UNK12A4 0x000012a4 +#define NVC0_3D_UNK12A4 0x000012a4 -#define NVC0_3D_UNK12AC 0x000012ac +#define NVC0_3D_UNK12AC 0x000012ac -#define NVC0_3D_UNK12C8 0x000012c8 +#define NVC0_3D_UNK12C8 0x000012c8 #define NVC0_3D_DEPTH_TEST_ENABLE 0x000012cc #define NVC0_3D_D3D_FILL_MODE 0x000012d0 #define NVC0_3D_D3D_FILL_MODE_POINT 0x00000001 -#define NVC0_3D_D3D_FILL_MODE_WIREFRAME 0x00000002 +#define NVC0_3D_D3D_FILL_MODE_WIREFRAME 0x00000002 #define NVC0_3D_D3D_FILL_MODE_SOLID 0x00000003 #define NVC0_3D_SHADE_MODEL 0x000012d4 @@ -812,7 +903,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_UNK12D8__ESIZE 0x00000004 #define NVC0_3D_UNK12D8__LEN 0x00000002 -#define NVC0_3D_UNK12E0 0x000012e0 +#define NVC0_3D_UNK12E0 0x000012e0 #define NVC0_3D_BLEND_INDEPENDENT 0x000012e4 @@ -823,51 +914,51 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VB_ELEMENT_U8_SETUP 0x00001300 #define NVC0_3D_VB_ELEMENT_U8_SETUP_OFFSET__MASK 0xc0000000 #define NVC0_3D_VB_ELEMENT_U8_SETUP_OFFSET__SHIFT 30 -#define NVC0_3D_VB_ELEMENT_U8_SETUP_COUNT__MASK 0x3fffffff +#define NVC0_3D_VB_ELEMENT_U8_SETUP_COUNT__MASK 0x3fffffff #define NVC0_3D_VB_ELEMENT_U8_SETUP_COUNT__SHIFT 0 #define NVC0_3D_VB_ELEMENT_U8 0x00001304 #define NVC0_3D_VB_ELEMENT_U8_I0__MASK 0x000000ff -#define NVC0_3D_VB_ELEMENT_U8_I0__SHIFT 0 +#define NVC0_3D_VB_ELEMENT_U8_I0__SHIFT 0 #define NVC0_3D_VB_ELEMENT_U8_I1__MASK 0x0000ff00 -#define NVC0_3D_VB_ELEMENT_U8_I1__SHIFT 8 +#define NVC0_3D_VB_ELEMENT_U8_I1__SHIFT 8 #define NVC0_3D_VB_ELEMENT_U8_I2__MASK 0x00ff0000 -#define NVC0_3D_VB_ELEMENT_U8_I2__SHIFT 16 +#define NVC0_3D_VB_ELEMENT_U8_I2__SHIFT 16 #define NVC0_3D_VB_ELEMENT_U8_I3__MASK 0xff000000 -#define NVC0_3D_VB_ELEMENT_U8_I3__SHIFT 24 +#define NVC0_3D_VB_ELEMENT_U8_I3__SHIFT 24 #define NVC0_3D_D3D_CULL_MODE 0x00001308 #define NVC0_3D_D3D_CULL_MODE_NONE 0x00000001 #define NVC0_3D_D3D_CULL_MODE_FRONT 0x00000002 #define NVC0_3D_D3D_CULL_MODE_BACK 0x00000003 -#define NVC0_3D_DEPTH_TEST_FUNC 0x0000130c +#define NVC0_3D_DEPTH_TEST_FUNC 0x0000130c #define NVC0_3D_DEPTH_TEST_FUNC_NEVER 0x00000200 #define NVC0_3D_DEPTH_TEST_FUNC_LESS 0x00000201 #define NVC0_3D_DEPTH_TEST_FUNC_EQUAL 0x00000202 #define NVC0_3D_DEPTH_TEST_FUNC_LEQUAL 0x00000203 -#define NVC0_3D_DEPTH_TEST_FUNC_GREATER 0x00000204 +#define NVC0_3D_DEPTH_TEST_FUNC_GREATER 0x00000204 #define NVC0_3D_DEPTH_TEST_FUNC_NOTEQUAL 0x00000205 #define NVC0_3D_DEPTH_TEST_FUNC_GEQUAL 0x00000206 #define NVC0_3D_DEPTH_TEST_FUNC_ALWAYS 0x00000207 #define NVC0_3D_ALPHA_TEST_REF 0x00001310 -#define NVC0_3D_ALPHA_TEST_FUNC 0x00001314 +#define NVC0_3D_ALPHA_TEST_FUNC 0x00001314 #define NVC0_3D_ALPHA_TEST_FUNC_NEVER 0x00000200 #define NVC0_3D_ALPHA_TEST_FUNC_LESS 0x00000201 #define NVC0_3D_ALPHA_TEST_FUNC_EQUAL 0x00000202 #define NVC0_3D_ALPHA_TEST_FUNC_LEQUAL 0x00000203 -#define NVC0_3D_ALPHA_TEST_FUNC_GREATER 0x00000204 +#define NVC0_3D_ALPHA_TEST_FUNC_GREATER 0x00000204 #define NVC0_3D_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205 #define NVC0_3D_ALPHA_TEST_FUNC_GEQUAL 0x00000206 #define NVC0_3D_ALPHA_TEST_FUNC_ALWAYS 0x00000207 -#define NVC0_3D_DRAW_TFB_STRIDE 0x00001318 +#define NVC0_3D_DRAW_TFB_STRIDE 0x00001318 #define NVC0_3D_DRAW_TFB_STRIDE__MIN 0x00000001 #define NVC0_3D_DRAW_TFB_STRIDE__MAX 0x00000fff -#define NVC0_3D_BLEND_COLOR(i0) (0x0000131c + 0x4*(i0)) +#define NVC0_3D_BLEND_COLOR(i0) (0x0000131c + 0x4*(i0)) #define NVC0_3D_BLEND_COLOR__ESIZE 0x00000004 #define NVC0_3D_BLEND_COLOR__LEN 0x00000004 @@ -884,6 +975,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_TEX_CACHE_CTL 0x00001338 #define NVC0_3D_TEX_CACHE_CTL_UNK0__MASK 0x00000007 #define NVC0_3D_TEX_CACHE_CTL_UNK0__SHIFT 0 +#define NVE4_3D_TEX_CACHE_CTL_UNK0 0x00000001 #define NVC0_3D_TEX_CACHE_CTL_ENTRY__MASK 0x03fffff0 #define NVC0_3D_TEX_CACHE_CTL_ENTRY__SHIFT 4 @@ -909,7 +1001,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_BLEND_FUNC_SRC_ALPHA 0x00001350 -#define NVC0_3D_UNK1354 0x00001354 +#define NVC0_3D_UNK1354 0x00001354 #define NVC0_3D_BLEND_FUNC_DST_ALPHA 0x00001358 @@ -928,8 +1020,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_STENCIL_FRONT_OP_FAIL_REPLACE 0x00001e01 #define NVC0_3D_STENCIL_FRONT_OP_FAIL_INCR 0x00001e02 #define NVC0_3D_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03 -#define NVC0_3D_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507 -#define NVC0_3D_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508 +#define NVC0_3D_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507 +#define NVC0_3D_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508 #define NVC0_3D_STENCIL_FRONT_OP_ZFAIL 0x00001388 #define NVC0_3D_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000 @@ -951,19 +1043,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507 #define NVC0_3D_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508 -#define NVC0_3D_STENCIL_FRONT_FUNC_FUNC 0x00001390 +#define NVC0_3D_STENCIL_FRONT_FUNC_FUNC 0x00001390 #define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200 #define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201 #define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202 #define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203 -#define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204 +#define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204 #define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205 #define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206 #define NVC0_3D_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207 #define NVC0_3D_STENCIL_FRONT_FUNC_REF 0x00001394 -#define NVC0_3D_STENCIL_FRONT_FUNC_MASK 0x00001398 +#define NVC0_3D_STENCIL_FRONT_FUNC_MASK 0x00001398 #define NVC0_3D_STENCIL_FRONT_MASK 0x0000139c @@ -987,9 +1079,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_LINE_WIDTH_ALIASED 0x000013b4 -#define NVC0_3D_UNK1418 0x00001418 +#define NVC0_3D_UNK1418 0x00001418 -#define NVC0_3D_UNK1420 0x00001420 +#define NVC0_3D_UNK1420 0x00001420 #define NVC0_3D_UNK1424_TSC_FLUSH 0x00001424 @@ -997,11 +1089,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VERTEX_ARRAY_FLUSH 0x0000142c -#define NVC0_3D_UNK1430 0x00001430 +#define NVC0_3D_UNK1430 0x00001430 #define NVC0_3D_UNK1430_UNK0 0x00000010 #define NVC0_3D_UNK1430_UNK1 0x00000100 -#define NVC0_3D_VB_ELEMENT_BASE 0x00001434 +#define NVC0_3D_VB_ELEMENT_BASE 0x00001434 #define NVC0_3D_VB_INSTANCE_BASE 0x00001438 @@ -1010,21 +1102,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_UNK143C_CLEAR_FLAGS_CLEAR_RECT__MASK 0x00000010 #define NVC0_3D_UNK143C_CLEAR_FLAGS_CLEAR_RECT__SHIFT 4 #define NVC0_3D_UNK143C_CLEAR_FLAGS_CLEAR_RECT_SCISSOR 0x00000000 -#define NVC0_3D_UNK143C_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT 0x00000000 +#define NVC0_3D_UNK143C_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT 0x00000000 -#define NVC0_3D_UNK1444 0x00001444 +#define NVC0_3D_UNK1444 0x00001444 -#define NVC0_3D_UNK1448 0x00001448 +#define NVC0_3D_UNK1448 0x00001448 -#define NVC0_3D_UNK144C 0x0000144c +#define NVC0_3D_UNK144C 0x0000144c -#define NVC0_3D_UNK1450 0x00001450 +#define NVC0_3D_UNK1450 0x00001450 -#define NVC0_3D_UNK1454 0x00001454 +#define NVC0_3D_UNK1454 0x00001454 -#define NVC0_3D_UNK1464 0x00001464 +#define NVC0_3D_UNK1464 0x00001464 -#define NVC0_3D_UNK1500 0x00001500 +#define NVC0_3D_UNK1500 0x00001500 #define NVC0_3D_CLIPID_HEIGHT 0x00001504 #define NVC0_3D_CLIPID_HEIGHT__MAX 0x00004000 @@ -1036,7 +1128,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CLIPID_FILL_RECT_HORIZ_HIGH__SHIFT 16 #define NVC0_3D_CLIPID_FILL_RECT_VERT 0x0000150c -#define NVC0_3D_CLIPID_FILL_RECT_VERT_LOW__MASK 0x0000ffff +#define NVC0_3D_CLIPID_FILL_RECT_VERT_LOW__MASK 0x0000ffff #define NVC0_3D_CLIPID_FILL_RECT_VERT_LOW__SHIFT 0 #define NVC0_3D_CLIPID_FILL_RECT_VERT_HIGH__MASK 0xffff0000 #define NVC0_3D_CLIPID_FILL_RECT_VERT_HIGH__SHIFT 16 @@ -1060,7 +1152,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_POINT_SPRITE_ENABLE 0x00001520 #define NVC0_3D_COUNTER_RESET 0x00001530 -#define NVC0_3D_COUNTER_RESET_SAMPLECNT 0x00000001 +#define NVC0_3D_COUNTER_RESET_SAMPLECNT 0x00000001 #define NVC0_3D_COUNTER_RESET_UNK02 0x00000002 #define NVC0_3D_COUNTER_RESET_UNK03 0x00000003 #define NVC0_3D_COUNTER_RESET_UNK04 0x00000004 @@ -1092,15 +1184,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_COND_ADDRESS_LOW 0x00001554 #define NVC0_3D_COND_MODE 0x00001558 -#define NVC0_3D_COND_MODE_NEVER 0x00000000 +#define NVC0_3D_COND_MODE_NEVER 0x00000000 #define NVC0_3D_COND_MODE_ALWAYS 0x00000001 #define NVC0_3D_COND_MODE_RES_NON_ZERO 0x00000002 -#define NVC0_3D_COND_MODE_EQUAL 0x00000003 +#define NVC0_3D_COND_MODE_EQUAL 0x00000003 #define NVC0_3D_COND_MODE_NOT_EQUAL 0x00000004 #define NVC0_3D_TSC_ADDRESS_HIGH 0x0000155c -#define NVC0_3D_TSC_ADDRESS_LOW 0x00001560 +#define NVC0_3D_TSC_ADDRESS_LOW 0x00001560 #define NVC0_3D_TSC_ADDRESS_LOW__ALIGN 0x00000020 #define NVC0_3D_TSC_LIMIT 0x00001564 @@ -1112,13 +1204,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_TIC_ADDRESS_HIGH 0x00001574 -#define NVC0_3D_TIC_ADDRESS_LOW 0x00001578 +#define NVC0_3D_TIC_ADDRESS_LOW 0x00001578 #define NVC0_3D_TIC_LIMIT 0x0000157c #define NVC0_3D_ZCULL_REGION 0x00001590 -#define NVC0_3D_STENCIL_TWO_SIDE_ENABLE 0x00001594 +#define NVC0_3D_STENCIL_TWO_SIDE_ENABLE 0x00001594 #define NVC0_3D_STENCIL_BACK_OP_FAIL 0x00001598 #define NVC0_3D_STENCIL_BACK_OP_FAIL_ZERO 0x00000000 @@ -1137,8 +1229,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01 #define NVC0_3D_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02 #define NVC0_3D_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03 -#define NVC0_3D_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507 -#define NVC0_3D_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508 +#define NVC0_3D_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507 +#define NVC0_3D_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508 #define NVC0_3D_STENCIL_BACK_OP_ZPASS 0x000015a0 #define NVC0_3D_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000 @@ -1147,8 +1239,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01 #define NVC0_3D_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02 #define NVC0_3D_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03 -#define NVC0_3D_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507 -#define NVC0_3D_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508 +#define NVC0_3D_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507 +#define NVC0_3D_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508 #define NVC0_3D_STENCIL_BACK_FUNC_FUNC 0x000015a4 #define NVC0_3D_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200 @@ -1156,7 +1248,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202 #define NVC0_3D_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203 #define NVC0_3D_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204 -#define NVC0_3D_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205 +#define NVC0_3D_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205 #define NVC0_3D_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206 #define NVC0_3D_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207 @@ -1166,10 +1258,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_POLYGON_OFFSET_UNITS 0x000015bc -#define NVC0_3D_UNK15C8 0x000015c8 +#define NVC0_3D_UNK15C8 0x000015c8 #define NVC0_3D_LAYER 0x000015cc -#define NVC0_3D_LAYER_IDX__MASK 0x0000ffff +#define NVC0_3D_LAYER_IDX__MASK 0x0000ffff #define NVC0_3D_LAYER_IDX__SHIFT 0 #define NVC0_3D_LAYER_USE_GP 0x00010000 @@ -1186,7 +1278,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_MULTISAMPLE_MODE_MS8_CS8 0x0000000a #define NVC0_3D_MULTISAMPLE_MODE_MS8_CS24 0x0000000b -#define NVC0_3D_EDGEFLAG_ENABLE 0x000015e4 +#define NVC0_3D_EDGEFLAG 0x000015e4 #define NVC0_3D_VB_ELEMENT_U32 0x000015e8 @@ -1197,14 +1289,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VB_ELEMENT_U16_SETUP_COUNT__SHIFT 0 #define NVC0_3D_VB_ELEMENT_U16 0x000015f0 -#define NVC0_3D_VB_ELEMENT_U16_I0__MASK 0x0000ffff +#define NVC0_3D_VB_ELEMENT_U16_I0__MASK 0x0000ffff #define NVC0_3D_VB_ELEMENT_U16_I0__SHIFT 0 -#define NVC0_3D_VB_ELEMENT_U16_I1__MASK 0xffff0000 +#define NVC0_3D_VB_ELEMENT_U16_I1__MASK 0xffff0000 #define NVC0_3D_VB_ELEMENT_U16_I1__SHIFT 16 #define NVC0_3D_VERTEX_BASE_HIGH 0x000015f4 -#define NVC0_3D_VERTEX_BASE_LOW 0x000015f8 +#define NVC0_3D_VERTEX_BASE_LOW 0x000015f8 #define NVC0_3D_ZCULL_WINDOW_OFFSET_X 0x000015fc @@ -1212,12 +1304,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_POINT_COORD_REPLACE 0x00001604 #define NVC0_3D_POINT_COORD_REPLACE_UNK0__MASK 0x00000003 -#define NVC0_3D_POINT_COORD_REPLACE_UNK0__SHIFT 0 +#define NVC0_3D_POINT_COORD_REPLACE_UNK0__SHIFT 0 #define NVC0_3D_POINT_COORD_REPLACE_UNK0_UNK0 0x00000000 #define NVC0_3D_POINT_COORD_REPLACE_UNK0_UNK1 0x00000001 #define NVC0_3D_POINT_COORD_REPLACE_UNK0_UNK2 0x00000002 #define NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN__MASK 0x00000004 -#define NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN__SHIFT 2 +#define NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN__SHIFT 2 #define NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT 0x00000000 #define NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT 0x00000004 #define NVC0_3D_POINT_COORD_REPLACE_ENABLE__MASK 0x00001ff8 @@ -1227,22 +1319,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CODE_ADDRESS_LOW 0x0000160c -#define NVC0_3D_UNK1610 0x00001610 +#define NVC0_3D_UNK1610 0x00001610 #define NVC0_3D_VERTEX_END_GL 0x00001614 #define NVC0_3D_VERTEX_END_GL_UNK0 0x00000001 -#define NVC0_3D_VERTEX_BEGIN_GL 0x00001618 -#define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE__MASK 0x0000ffff +#define NVC0_3D_VERTEX_BEGIN_GL 0x00001618 +#define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE__MASK 0x0000ffff #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE__SHIFT 0 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS 0x00000000 -#define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_LINES 0x00000001 +#define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_LINES 0x00000001 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_LINE_LOOP 0x00000002 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_LINE_STRIP 0x00000003 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES 0x00000004 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLE_STRIP 0x00000005 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLE_FAN 0x00000006 -#define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_QUADS 0x00000007 +#define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_QUADS 0x00000007 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_QUAD_STRIP 0x00000008 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POLYGON 0x00000009 #define NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_LINES_ADJACENCY 0x0000000a @@ -1256,22 +1348,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VERTEX_BEGIN_GL_UNK29 0x20000000 #define NVC0_3D_VERTEX_BEGIN_GL_UNK30 0x40000000 -#define NVC0_3D_UNK161C 0x0000161c -#define NVC0_3D_UNK161C_UNK0 0x00000001 -#define NVC0_3D_UNK161C_UNK4__MASK 0x00000ff0 -#define NVC0_3D_UNK161C_UNK4__SHIFT 4 +#define NVC0_3D_VERTEX_ID_REPLACE 0x0000161c +#define NVC0_3D_VERTEX_ID_REPLACE_ENABLE 0x00000001 +#define NVC0_3D_VERTEX_ID_REPLACE_SOURCE__MASK 0x00000ff0 +#define NVC0_3D_VERTEX_ID_REPLACE_SOURCE__SHIFT 4 -#define NVC0_3D_UNK1620 0x00001620 +#define NVC0_3D_UNK1620 0x00001620 -#define NVC0_3D_UNK1624 0x00001624 +#define NVC0_3D_UNK1624 0x00001624 -#define NVC0_3D_UNK162C 0x0000162c +#define NVC0_3D_UNK162C 0x0000162c -#define NVC0_3D_UNK1634 0x00001634 +#define NVC0_3D_UNK1634 0x00001634 -#define NVC0_3D_UNK1638 0x00001638 +#define NVC0_3D_UNK1638 0x00001638 -#define NVC0_3D_UNK163C 0x0000163c +#define NVC0_3D_UNK163C 0x0000163c #define NVC0_3D_VERTEX_DATA 0x00001640 @@ -1279,8 +1371,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_PRIM_RESTART_INDEX 0x00001648 -#define NVC0_3D_VP_GP_BUILTIN_ATTR_EN 0x0000164c -#define NVC0_3D_VP_GP_BUILTIN_ATTR_EN_UNK12 0x00001000 +#define NVC0_3D_VERTEX_ID_GEN_MODE 0x0000164c +#define NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START 0x00001000 #define NVC0_3D_POINT_SMOOTH_ENABLE 0x00001658 @@ -1294,7 +1386,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_LINE_SMOOTH_BLUR 0x00001668 #define NVC0_3D_LINE_SMOOTH_BLUR_LOW 0x00000000 -#define NVC0_3D_LINE_SMOOTH_BLUR_MEDIUM 0x00000001 +#define NVC0_3D_LINE_SMOOTH_BLUR_MEDIUM 0x00000001 #define NVC0_3D_LINE_SMOOTH_BLUR_HIGH 0x00000002 #define NVC0_3D_LINE_STIPPLE_ENABLE 0x0000166c @@ -1319,19 +1411,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_POLYGON_STIPPLE_ENABLE 0x0000168c -#define NVC0_3D_UNK1690 0x00001690 +#define NVC0_3D_UNK1690 0x00001690 #define NVC0_3D_UNK1690_ALWAYS_DERIV 0x00000001 #define NVC0_3D_UNK1690_UNK16 0x00010000 -#define NVC0_3D_UNK169C 0x0000169c +#define NVE4_3D_UNK1690 0x00001690 + +#define NVC0_3D_UNK169C 0x0000169c -#define NVC0_3D_UNK16A0 0x000016a0 +#define NVC0_3D_UNK16A0 0x000016a0 -#define NVC0_3D_UNK16A4 0x000016a4 +#define NVC0_3D_UNK16A4 0x000016a4 -#define NVC0_3D_UNK16A8 0x000016a8 +#define NVC0_3D_UNK16A8 0x000016a8 -#define NVC0_3D_UNK16B4 0x000016b4 +#define NVC0_3D_UNK16B4 0x000016b4 #define NVC0_3D_UNK16B4_UNK0 0x00000001 #define NVC0_3D_UNK16B4_UNK1 0x00000002 @@ -1339,11 +1433,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_POLYGON_STIPPLE_PATTERN__ESIZE 0x00000004 #define NVC0_3D_POLYGON_STIPPLE_PATTERN__LEN 0x00000020 -#define NVC0_3D_UNK1790 0x00001790 +#define NVC0_3D_UNK1790 0x00001790 -#define NVC0_3D_UNK1794 0x00001794 +#define NVC0_3D_UNK1794 0x00001794 -#define NVC0_3D_ZETA_BASE_LAYER 0x0000179c +#define NVC0_3D_ZETA_BASE_LAYER 0x0000179c #define NVC0_3D_VERTEX_QUARANTINE_ADDRESS_HIGH 0x000017bc @@ -1363,7 +1457,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_INDEX_ARRAY_LIMIT_LOW 0x000017d4 #define NVC0_3D_INDEX_FORMAT 0x000017d8 -#define NVC0_3D_INDEX_FORMAT_I8 0x00000000 +#define NVC0_3D_INDEX_FORMAT_I8 0x00000000 #define NVC0_3D_INDEX_FORMAT_I16 0x00000001 #define NVC0_3D_INDEX_FORMAT_I32 0x00000002 @@ -1393,23 +1487,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_FRONT_FACE_CCW 0x00000901 #define NVC0_3D_CULL_FACE 0x00001920 -#define NVC0_3D_CULL_FACE_FRONT 0x00000404 +#define NVC0_3D_CULL_FACE_FRONT 0x00000404 #define NVC0_3D_CULL_FACE_BACK 0x00000405 #define NVC0_3D_CULL_FACE_FRONT_AND_BACK 0x00000408 -#define NVC0_3D_LINE_LAST_PIXEL 0x00001924 +#define NVC0_3D_PIXEL_CENTER_INTEGER 0x00001924 #define NVC0_3D_VIEWPORT_TRANSFORM_EN 0x0000192c -#define NVC0_3D_UNK1930 0x00001930 +#define NVC0_3D_UNK1930 0x00001930 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL 0x0000193c -#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK0 0x00000001 +#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1 0x00000001 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1__MASK 0x00000006 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1__SHIFT 1 -#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK0 0x00000000 -#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 0x00000002 -#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK2 0x00000004 +#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK0 0x00000000 +#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 0x00000002 +#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK2 0x00000004 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR 0x00000008 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR 0x00000010 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK7 0x00000080 @@ -1455,13 +1549,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CLIP_DISTANCE_MODE_7_CLIP 0x00000000 #define NVC0_3D_CLIP_DISTANCE_MODE_7_CULL 0x10000000 -#define NVC0_3D_UNK1944 0x00001944 +#define NVC0_3D_UNK1944 0x00001944 -#define NVC0_3D_UNK1948 0x00001948 +#define NVC0_3D_UNK1948 0x00001948 #define NVC0_3D_CLIP_RECTS_EN 0x0000194c -#define NVC0_3D_CLIP_RECTS_MODE 0x00001950 +#define NVC0_3D_CLIP_RECTS_MODE 0x00001950 #define NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY 0x00000000 #define NVC0_3D_CLIP_RECTS_MODE_OUTSIDE_ALL 0x00000001 #define NVC0_3D_CLIP_RECTS_MODE_NEVER 0x00000002 @@ -1472,9 +1566,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_ZCULL_UNK1968_TESTS_ENABLE 0x00000001 #define NVC0_3D_ZCULL_UNK1968_UNK4 0x00000010 -#define NVC0_3D_ZCULL_TEST_MASK 0x0000196c -#define NVC0_3D_ZCULL_TEST_MASK_FAIL_GT_PASS_LT 0x00000001 -#define NVC0_3D_ZCULL_TEST_MASK_PASS_GT_FAIL_LT 0x00000010 +#define NVC0_3D_ZCULL_TEST_MASK 0x0000196c +#define NVC0_3D_ZCULL_TEST_MASK_FAIL_GT_PASS_LT 0x00000001 +#define NVC0_3D_ZCULL_TEST_MASK_PASS_GT_FAIL_LT 0x00000010 #define NVC0_3D_UNK1970_D3D 0x00001970 #define NVC0_3D_UNK1970_D3D_POINTS 0x00000001 @@ -1484,11 +1578,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_UNK1970_D3D_TRIANGLE_STRIP 0x00000005 #define NVC0_3D_UNK1970_D3D_LINES_ADJACENCY 0x0000000a #define NVC0_3D_UNK1970_D3D_LINE_STRIP_ADJACENCY 0x0000000b -#define NVC0_3D_UNK1970_D3D_TRIANGLES_ADJACENCY 0x0000000c +#define NVC0_3D_UNK1970_D3D_TRIANGLES_ADJACENCY 0x0000000c #define NVC0_3D_UNK1970_D3D_TRIANGLE_STRIP_ADJACENCY 0x0000000d #define NVC0_3D_UNK1970_D3D_PATCHES 0x0000000e -#define NVC0_3D_UNK1978 0x00001978 +#define NVC0_3D_UNK1978 0x00001978 #define NVC0_3D_CLIPID_ENABLE 0x0000197c @@ -1498,11 +1592,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CLIPID_ID 0x00001984 -#define NVC0_3D_DEPTH_BOUNDS_EN 0x000019bc +#define NVC0_3D_DEPTH_BOUNDS_EN 0x000019bc -#define NVC0_3D_UNK19C0 0x000019c0 +#define NVC0_3D_UNK19C0 0x000019c0 -#define NVC0_3D_LOGIC_OP_ENABLE 0x000019c4 +#define NVC0_3D_LOGIC_OP_ENABLE 0x000019c4 #define NVC0_3D_LOGIC_OP 0x000019c8 #define NVC0_3D_LOGIC_OP_CLEAR 0x00001500 @@ -1515,7 +1609,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_LOGIC_OP_OR 0x00001507 #define NVC0_3D_LOGIC_OP_NOR 0x00001508 #define NVC0_3D_LOGIC_OP_EQUIV 0x00001509 -#define NVC0_3D_LOGIC_OP_INVERT 0x0000150a +#define NVC0_3D_LOGIC_OP_INVERT 0x0000150a #define NVC0_3D_LOGIC_OP_OR_REVERSE 0x0000150b #define NVC0_3D_LOGIC_OP_COPY_INVERTED 0x0000150c #define NVC0_3D_LOGIC_OP_OR_INVERTED 0x0000150d @@ -1525,14 +1619,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_ZETA_COMP_ENABLE 0x000019cc #define NVC0_3D_CLEAR_BUFFERS 0x000019d0 -#define NVC0_3D_CLEAR_BUFFERS_Z 0x00000001 -#define NVC0_3D_CLEAR_BUFFERS_S 0x00000002 -#define NVC0_3D_CLEAR_BUFFERS_R 0x00000004 -#define NVC0_3D_CLEAR_BUFFERS_G 0x00000008 -#define NVC0_3D_CLEAR_BUFFERS_B 0x00000010 -#define NVC0_3D_CLEAR_BUFFERS_A 0x00000020 +#define NVC0_3D_CLEAR_BUFFERS_Z 0x00000001 +#define NVC0_3D_CLEAR_BUFFERS_S 0x00000002 +#define NVC0_3D_CLEAR_BUFFERS_R 0x00000004 +#define NVC0_3D_CLEAR_BUFFERS_G 0x00000008 +#define NVC0_3D_CLEAR_BUFFERS_B 0x00000010 +#define NVC0_3D_CLEAR_BUFFERS_A 0x00000020 #define NVC0_3D_CLEAR_BUFFERS_RT__MASK 0x000003c0 -#define NVC0_3D_CLEAR_BUFFERS_RT__SHIFT 6 +#define NVC0_3D_CLEAR_BUFFERS_RT__SHIFT 6 #define NVC0_3D_CLEAR_BUFFERS_LAYER__MASK 0x001ffc00 #define NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT 10 @@ -1544,7 +1638,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_COLOR_MASK(i0) (0x00001a00 + 0x4*(i0)) #define NVC0_3D_COLOR_MASK__ESIZE 0x00000004 -#define NVC0_3D_COLOR_MASK__LEN 0x00000008 +#define NVC0_3D_COLOR_MASK__LEN 0x00000008 #define NVC0_3D_COLOR_MASK_R 0x0000000f #define NVC0_3D_COLOR_MASK_G 0x000000f0 #define NVC0_3D_COLOR_MASK_B 0x00000f00 @@ -1568,11 +1662,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_QUERY_GET_MODE_WRITE 0x00000000 #define NVC0_3D_QUERY_GET_MODE_SYNC 0x00000001 #define NVC0_3D_QUERY_GET_MODE_WRITE_UNK2 0x00000002 -#define NVC0_3D_QUERY_GET_MODE_WRITE_INTR_UNK1 0x00000003 +#define NVC0_3D_QUERY_GET_MODE_WRITE_INTR_NRHOST 0x00000003 #define NVC0_3D_QUERY_GET_UNK2 0x00000004 -#define NVC0_3D_QUERY_GET_FENCE 0x00000010 +#define NVC0_3D_QUERY_GET_FENCE 0x00000010 #define NVC0_3D_QUERY_GET_STREAM__MASK 0x000000e0 -#define NVC0_3D_QUERY_GET_STREAM__SHIFT 5 +#define NVC0_3D_QUERY_GET_STREAM__SHIFT 5 #define NVC0_3D_QUERY_GET_UNK8 0x00000100 #define NVC0_3D_QUERY_GET_UNIT__MASK 0x0000f000 #define NVC0_3D_QUERY_GET_UNIT__SHIFT 12 @@ -1581,19 +1675,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_QUERY_GET_SYNC_COND_NEQUAL 0x00000000 #define NVC0_3D_QUERY_GET_SYNC_COND_GREATER 0x00010000 #define NVC0_3D_QUERY_GET_INTR 0x00100000 -#define NVC0_3D_QUERY_GET_UNK21 0x00200000 +#define NVC0_3D_QUERY_GET_UNK21 0x00200000 #define NVC0_3D_QUERY_GET_SELECT__MASK 0x0f800000 -#define NVC0_3D_QUERY_GET_SELECT__SHIFT 23 +#define NVC0_3D_QUERY_GET_SELECT__SHIFT 23 #define NVC0_3D_QUERY_GET_SELECT_ZERO 0x00000000 #define NVC0_3D_QUERY_GET_SELECT_SAMPLECNT 0x01000000 #define NVC0_3D_QUERY_GET_SELECT_EMITTED_PRIMS 0x05800000 #define NVC0_3D_QUERY_GET_SELECT_GENERATED_PRIMS 0x09000000 -#define NVC0_3D_QUERY_GET_SHORT 0x10000000 +#define NVC0_3D_QUERY_GET_SHORT 0x10000000 #define NVC0_3D_VERTEX_ARRAY_FETCH(i0) (0x00001c00 + 0x10*(i0)) #define NVC0_3D_VERTEX_ARRAY_FETCH__ESIZE 0x00000010 -#define NVC0_3D_VERTEX_ARRAY_FETCH__LEN 0x00000020 -#define NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__MASK 0x00000fff +#define NVC0_3D_VERTEX_ARRAY_FETCH__LEN 0x00000020 +#define NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__MASK 0x00000fff #define NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT 0 #define NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE 0x00001000 @@ -1615,16 +1709,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_IBLEND_SEPARATE_ALPHA(i0) (0x00001e00 + 0x20*(i0)) -#define NVC0_3D_IBLEND_EQUATION_RGB(i0) (0x00001e04 + 0x20*(i0)) +#define NVC0_3D_IBLEND_EQUATION_RGB(i0) (0x00001e04 + 0x20*(i0)) #define NVC0_3D_IBLEND_EQUATION_RGB_FUNC_ADD 0x00008006 -#define NVC0_3D_IBLEND_EQUATION_RGB_MIN 0x00008007 -#define NVC0_3D_IBLEND_EQUATION_RGB_MAX 0x00008008 +#define NVC0_3D_IBLEND_EQUATION_RGB_MIN 0x00008007 +#define NVC0_3D_IBLEND_EQUATION_RGB_MAX 0x00008008 #define NVC0_3D_IBLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a #define NVC0_3D_IBLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b -#define NVC0_3D_IBLEND_FUNC_SRC_RGB(i0) (0x00001e08 + 0x20*(i0)) +#define NVC0_3D_IBLEND_FUNC_SRC_RGB(i0) (0x00001e08 + 0x20*(i0)) -#define NVC0_3D_IBLEND_FUNC_DST_RGB(i0) (0x00001e0c + 0x20*(i0)) +#define NVC0_3D_IBLEND_FUNC_DST_RGB(i0) (0x00001e0c + 0x20*(i0)) #define NVC0_3D_IBLEND_EQUATION_ALPHA(i0) (0x00001e10 + 0x20*(i0)) #define NVC0_3D_IBLEND_EQUATION_ALPHA_FUNC_ADD 0x00008006 @@ -1647,11 +1741,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_SP(i0) (0x00002000 + 0x40*(i0)) #define NVC0_3D_SP__ESIZE 0x00000040 -#define NVC0_3D_SP__LEN 0x00000006 +#define NVC0_3D_SP__LEN 0x00000006 #define NVC0_3D_SP_SELECT(i0) (0x00002000 + 0x40*(i0)) #define NVC0_3D_SP_SELECT_ENABLE 0x00000001 -#define NVC0_3D_SP_SELECT_PROGRAM__MASK 0x000000f0 +#define NVC0_3D_SP_SELECT_PROGRAM__MASK 0x000000f0 #define NVC0_3D_SP_SELECT_PROGRAM__SHIFT 4 #define NVC0_3D_SP_SELECT_PROGRAM_VP_A 0x00000000 #define NVC0_3D_SP_SELECT_PROGRAM_VP_B 0x00000010 @@ -1660,7 +1754,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_SP_SELECT_PROGRAM_GP 0x00000040 #define NVC0_3D_SP_SELECT_PROGRAM_FP 0x00000050 -#define NVC0_3D_SP_START_ID(i0) (0x00002004 + 0x40*(i0)) +#define NVC0_3D_SP_START_ID(i0) (0x00002004 + 0x40*(i0)) #define NVC0_3D_SP_UNK08(i0) (0x00002008 + 0x40*(i0)) @@ -1674,18 +1768,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_SP_TYPE_FP 0x00000004 #define NVC0_3D_SP_UNK14(i0, i1) (0x00002014 + 0x40*(i0) + 0x4*(i1)) -#define NVC0_3D_SP_UNK14__ESIZE 0x00000004 +#define NVC0_3D_SP_UNK14__ESIZE 0x00000004 #define NVC0_3D_SP_UNK14__LEN 0x00000004 #define NVC0_3D_TEX_LIMITS(i0) (0x00002200 + 0x10*(i0)) #define NVC0_3D_TEX_LIMITS__ESIZE 0x00000010 -#define NVC0_3D_TEX_LIMITS__LEN 0x00000005 +#define NVC0_3D_TEX_LIMITS__LEN 0x00000005 #define NVC0_3D_TEX_LIMITS_SAMPLERS_LOG2__MASK 0x0000000f -#define NVC0_3D_TEX_LIMITS_SAMPLERS_LOG2__SHIFT 0 +#define NVC0_3D_TEX_LIMITS_SAMPLERS_LOG2__SHIFT 0 #define NVC0_3D_TEX_LIMITS_SAMPLERS_LOG2__MIN 0x00000000 #define NVC0_3D_TEX_LIMITS_SAMPLERS_LOG2__MAX 0x00000004 #define NVC0_3D_TEX_LIMITS_TEXTURES_LOG2__MASK 0x000000f0 -#define NVC0_3D_TEX_LIMITS_TEXTURES_LOG2__SHIFT 4 +#define NVC0_3D_TEX_LIMITS_TEXTURES_LOG2__SHIFT 4 #define NVC0_3D_TEX_LIMITS_TEXTURES_LOG2__MIN 0x00000000 #define NVC0_3D_TEX_LIMITS_TEXTURES_LOG2__MAX 0x00000007 @@ -1698,12 +1792,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_UNK2208__LEN 0x00000005 #define NVC0_3D_FIRMWARE(i0) (0x00002300 + 0x4*(i0)) -#define NVC0_3D_FIRMWARE__ESIZE 0x00000004 +#define NVC0_3D_FIRMWARE__ESIZE 0x00000004 #define NVC0_3D_FIRMWARE__LEN 0x00000020 -#define NVC0_3D_CB_SIZE 0x00002380 +#define NVC0_3D_CB_SIZE 0x00002380 -#define NVC0_3D_CB_ADDRESS_HIGH 0x00002384 +#define NVC0_3D_CB_ADDRESS_HIGH 0x00002384 #define NVC0_3D_CB_ADDRESS_LOW 0x00002388 @@ -1714,20 +1808,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CB_DATA__LEN 0x00000010 #define NVC0_3D_BIND_TSC(i0) (0x00002400 + 0x20*(i0)) -#define NVC0_3D_BIND_TSC__ESIZE 0x00000020 +#define NVC0_3D_BIND_TSC__ESIZE 0x00000020 #define NVC0_3D_BIND_TSC__LEN 0x00000005 -#define NVC0_3D_BIND_TSC_ACTIVE 0x00000001 +#define NVC0_3D_BIND_TSC_ACTIVE 0x00000001 #define NVC0_3D_BIND_TSC_SAMPLER__MASK 0x00000ff0 -#define NVC0_3D_BIND_TSC_SAMPLER__SHIFT 4 +#define NVC0_3D_BIND_TSC_SAMPLER__SHIFT 4 #define NVC0_3D_BIND_TSC_TSC__MASK 0x01fff000 #define NVC0_3D_BIND_TSC_TSC__SHIFT 12 #define NVC0_3D_BIND_TIC(i0) (0x00002404 + 0x20*(i0)) -#define NVC0_3D_BIND_TIC__ESIZE 0x00000020 +#define NVC0_3D_BIND_TIC__ESIZE 0x00000020 #define NVC0_3D_BIND_TIC__LEN 0x00000005 -#define NVC0_3D_BIND_TIC_ACTIVE 0x00000001 +#define NVC0_3D_BIND_TIC_ACTIVE 0x00000001 #define NVC0_3D_BIND_TIC_TEXTURE__MASK 0x000001fe -#define NVC0_3D_BIND_TIC_TEXTURE__SHIFT 1 +#define NVC0_3D_BIND_TIC_TEXTURE__SHIFT 1 #define NVC0_3D_BIND_TIC_TIC__MASK 0x7ffffe00 #define NVC0_3D_BIND_TIC_TIC__SHIFT 9 @@ -1735,7 +1829,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_BIND_TSC2__ESIZE 0x00000020 #define NVC0_3D_BIND_TSC2__LEN 0x00000005 #define NVC0_3D_BIND_TSC2_ACTIVE 0x00000001 -#define NVC0_3D_BIND_TSC2_SAMPLER__MASK 0x00000010 +#define NVC0_3D_BIND_TSC2_SAMPLER__MASK 0x00000010 #define NVC0_3D_BIND_TSC2_SAMPLER__SHIFT 4 #define NVC0_3D_BIND_TSC2_TSC__MASK 0x01fff000 #define NVC0_3D_BIND_TSC2_TSC__SHIFT 12 @@ -1744,11 +1838,27 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_BIND_TIC2__ESIZE 0x00000020 #define NVC0_3D_BIND_TIC2__LEN 0x00000005 #define NVC0_3D_BIND_TIC2_ACTIVE 0x00000001 -#define NVC0_3D_BIND_TIC2_TEXTURE__MASK 0x00000002 +#define NVC0_3D_BIND_TIC2_TEXTURE__MASK 0x00000002 #define NVC0_3D_BIND_TIC2_TEXTURE__SHIFT 1 #define NVC0_3D_BIND_TIC2_TIC__MASK 0x7ffffe00 #define NVC0_3D_BIND_TIC2_TIC__SHIFT 9 +#define NVE4_3D_UNK2400_TSC(i0) (0x00002400 + 0x20*(i0)) +#define NVE4_3D_UNK2400_TSC__ESIZE 0x00000020 +#define NVE4_3D_UNK2400_TSC__LEN 0x00000005 + +#define NVE4_3D_UNK2400_TIC(i0) (0x00002404 + 0x20*(i0)) +#define NVE4_3D_UNK2400_TIC__ESIZE 0x00000020 +#define NVE4_3D_UNK2400_TIC__LEN 0x00000005 + +#define NVE4_3D_UNK2400_TSC2(i0) (0x00002408 + 0x20*(i0)) +#define NVE4_3D_UNK2400_TSC2__ESIZE 0x00000020 +#define NVE4_3D_UNK2400_TSC2__LEN 0x00000005 + +#define NVE4_3D_UNK2400_TIC2(i0) (0x0000240c + 0x20*(i0)) +#define NVE4_3D_UNK2400_TIC2__ESIZE 0x00000020 +#define NVE4_3D_UNK2400_TIC2__LEN 0x00000005 + #define NVC0_3D_CB_BIND(i0) (0x00002410 + 0x20*(i0)) #define NVC0_3D_CB_BIND__ESIZE 0x00000020 #define NVC0_3D_CB_BIND__LEN 0x00000005 @@ -1778,6 +1888,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VERT_COLOR_CLAMP_EN 0x00002600 +#define NVE4_3D_UNK2604 0x00002604 + +#define NVE4_3D_TEX_CB_INDEX 0x00002608 +#define NVE4_3D_TEX_CB_INDEX__MIN 0x00000000 +#define NVE4_3D_TEX_CB_INDEX__MAX 0x00000010 + +#define NVE4_3D_UNK260C 0x0000260c + #define NVC0_3D_IMAGE(i0) (0x00002700 + 0x20*(i0)) #define NVC0_3D_IMAGE__ESIZE 0x00000020 #define NVC0_3D_IMAGE__LEN 0x00000008 @@ -1786,7 +1904,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_IMAGE_ADDRESS_LOW(i0) (0x00002704 + 0x20*(i0)) -#define NVC0_3D_IMAGE_WIDTH(i0) (0x00002708 + 0x20*(i0)) +#define NVC0_3D_IMAGE_WIDTH(i0) (0x00002708 + 0x20*(i0)) #define NVC0_3D_IMAGE_HEIGHT(i0) (0x0000270c + 0x20*(i0)) #define NVC0_3D_IMAGE_HEIGHT_HEIGHT__MASK 0x0000ffff @@ -1796,72 +1914,141 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_IMAGE_FORMAT(i0) (0x00002710 + 0x20*(i0)) #define NVC0_3D_IMAGE_FORMAT_UNK0 0x00000001 -#define NVC0_3D_IMAGE_FORMAT_FORMAT_COLOR__MASK 0x00000ff0 +#define NVC0_3D_IMAGE_FORMAT_FORMAT_COLOR__MASK 0x00000ff0 #define NVC0_3D_IMAGE_FORMAT_FORMAT_COLOR__SHIFT 4 #define NVC0_3D_IMAGE_FORMAT_FORMAT_ZETA__MASK 0x0001f000 -#define NVC0_3D_IMAGE_FORMAT_FORMAT_ZETA__SHIFT 12 +#define NVC0_3D_IMAGE_FORMAT_FORMAT_ZETA__SHIFT 12 #define NVC0_3D_IMAGE_TILE_MODE(i0) (0x00002714 + 0x20*(i0)) #define NVC0_3D_TFB_VARYING_LOCS(i0, i1) (0x00002800 + 0x80*(i0) + 0x4*(i1)) -#define NVC0_3D_TFB_VARYING_LOCS__ESIZE 0x00000004 +#define NVC0_3D_TFB_VARYING_LOCS__ESIZE 0x00000004 #define NVC0_3D_TFB_VARYING_LOCS__LEN 0x00000020 -#define NVC0_3D_PM_SET(i0) (0x0000335c + 0x4*(i0)) -#define NVC0_3D_PM_SET__ESIZE 0x00000004 -#define NVC0_3D_PM_SET__LEN 0x00000008 - -#define NVC0_3D_PM_UNK337C(i0) (0x0000337c + 0x4*(i0)) -#define NVC0_3D_PM_UNK337C__ESIZE 0x00000004 -#define NVC0_3D_PM_UNK337C__LEN 0x00000008 - -#define NVC0_3D_PM_UNK339C(i0) (0x0000339c + 0x4*(i0)) -#define NVC0_3D_PM_UNK339C__ESIZE 0x00000004 -#define NVC0_3D_PM_UNK339C__LEN 0x00000008 -#define NVC0_3D_PM_UNK339C_0__MASK 0x00000007 -#define NVC0_3D_PM_UNK339C_0__SHIFT 0 -#define NVC0_3D_PM_UNK339C_1__MASK 0x00000070 -#define NVC0_3D_PM_UNK339C_1__SHIFT 4 -#define NVC0_3D_PM_UNK339C_2__MASK 0x00000700 -#define NVC0_3D_PM_UNK339C_2__SHIFT 8 -#define NVC0_3D_PM_UNK339C_3__MASK 0x00007000 -#define NVC0_3D_PM_UNK339C_3__SHIFT 12 -#define NVC0_3D_PM_UNK339C_4__MASK 0x00070000 -#define NVC0_3D_PM_UNK339C_4__SHIFT 16 -#define NVC0_3D_PM_UNK339C_5__MASK 0x00700000 -#define NVC0_3D_PM_UNK339C_5__SHIFT 20 -#define NVC0_3D_PM_UNK339C_6__MASK 0x07000000 -#define NVC0_3D_PM_UNK339C_6__SHIFT 24 -#define NVC0_3D_PM_UNK339C_7__MASK 0x70000000 -#define NVC0_3D_PM_UNK339C_7__SHIFT 28 - -#define NVC0_3D_PM_UNK33BC(i0) (0x000033bc + 0x4*(i0)) -#define NVC0_3D_PM_UNK33BC__ESIZE 0x00000004 -#define NVC0_3D_PM_UNK33BC__LEN 0x00000008 -#define NVC0_3D_PM_UNK33BC_0 0x00000001 -#define NVC0_3D_PM_UNK33BC_4__MASK 0x0000fff0 -#define NVC0_3D_PM_UNK33BC_4__SHIFT 4 - -#define NVC0_3D_PM_UNK33DC 0x000033dc - -#define NVC0_3D_VERTEX_ARRAY_SELECT 0x00003820 - -#define NVC0_3D_BLEND_ENABLES 0x00003858 - -#define NVC0_3D_POLYGON_MODE_FRONT 0x00003868 -#define NVC0_3D_POLYGON_MODE_FRONT_POINT 0x00001b00 -#define NVC0_3D_POLYGON_MODE_FRONT_LINE 0x00001b01 -#define NVC0_3D_POLYGON_MODE_FRONT_FILL 0x00001b02 - -#define NVC0_3D_POLYGON_MODE_BACK 0x00003870 -#define NVC0_3D_POLYGON_MODE_BACK_POINT 0x00001b00 -#define NVC0_3D_POLYGON_MODE_BACK_LINE 0x00001b01 -#define NVC0_3D_POLYGON_MODE_BACK_FILL 0x00001b02 - -#define NVC0_3D_GP_SELECT 0x00003878 - -#define NVC0_3D_TEP_SELECT 0x00003880 - - -#endif /* _HOME_SKEGGSB_GIT_ENVYTOOLS_RNNDB_NVC0_3D_XML */ +#define NVC0_3D_MP_PM_SET(i0) (0x0000335c + 0x4*(i0)) +#define NVC0_3D_MP_PM_SET__ESIZE 0x00000004 +#define NVC0_3D_MP_PM_SET__LEN 0x00000008 + +#define NVC0_3D_MP_PM_SIGSEL(i0) (0x0000337c + 0x4*(i0)) +#define NVC0_3D_MP_PM_SIGSEL__ESIZE 0x00000004 +#define NVC0_3D_MP_PM_SIGSEL__LEN 0x00000008 + +#define NVE4_3D_MP_PM_A_SIGSEL(i0) (0x0000337c + 0x4*(i0)) +#define NVE4_3D_MP_PM_A_SIGSEL__ESIZE 0x00000004 +#define NVE4_3D_MP_PM_A_SIGSEL__LEN 0x00000004 +#define NVE4_3D_MP_PM_A_SIGSEL_NONE 0x00000000 +#define NVE4_3D_MP_PM_A_SIGSEL_USER 0x00000001 +#define NVE4_3D_MP_PM_A_SIGSEL_LAUNCH 0x00000003 +#define NVE4_3D_MP_PM_A_SIGSEL_EXEC 0x00000004 +#define NVE4_3D_MP_PM_A_SIGSEL_ISSUE 0x00000005 +#define NVE4_3D_MP_PM_A_SIGSEL_LDST 0x0000001b +#define NVE4_3D_MP_PM_A_SIGSEL_BRANCH 0x0000001c + +#define NVE4_3D_MP_PM_B_SIGSEL(i0) (0x0000338c + 0x4*(i0)) +#define NVE4_3D_MP_PM_B_SIGSEL__ESIZE 0x00000004 +#define NVE4_3D_MP_PM_B_SIGSEL__LEN 0x00000004 +#define NVE4_3D_MP_PM_B_SIGSEL_NONE 0x00000000 +#define NVE4_3D_MP_PM_B_SIGSEL_WARP 0x00000002 +#define NVE4_3D_MP_PM_B_SIGSEL_REPLAY 0x00000008 +#define NVE4_3D_MP_PM_B_SIGSEL_TRANSACTION 0x0000000e +#define NVE4_3D_MP_PM_B_SIGSEL_L1 0x00000010 +#define NVE4_3D_MP_PM_B_SIGSEL_MEM 0x00000011 + +#define NVC0_3D_MP_PM_SRCSEL(i0) (0x0000339c + 0x4*(i0)) +#define NVC0_3D_MP_PM_SRCSEL__ESIZE 0x00000004 +#define NVC0_3D_MP_PM_SRCSEL__LEN 0x00000008 +#define NVC0_3D_MP_PM_SRCSEL_GRP0__MASK 0x00000007 +#define NVC0_3D_MP_PM_SRCSEL_GRP0__SHIFT 0 +#define NVC0_3D_MP_PM_SRCSEL_SIG0__MASK 0x00000070 +#define NVC0_3D_MP_PM_SRCSEL_SIG0__SHIFT 4 +#define NVC0_3D_MP_PM_SRCSEL_GRP1__MASK 0x00000700 +#define NVC0_3D_MP_PM_SRCSEL_GRP1__SHIFT 8 +#define NVC0_3D_MP_PM_SRCSEL_SIG1__MASK 0x00007000 +#define NVC0_3D_MP_PM_SRCSEL_SIG1__SHIFT 12 +#define NVC0_3D_MP_PM_SRCSEL_GRP2__MASK 0x00070000 +#define NVC0_3D_MP_PM_SRCSEL_GRP2__SHIFT 16 +#define NVC0_3D_MP_PM_SRCSEL_SIG2__MASK 0x00700000 +#define NVC0_3D_MP_PM_SRCSEL_SIG2__SHIFT 20 +#define NVC0_3D_MP_PM_SRCSEL_GRP3__MASK 0x07000000 +#define NVC0_3D_MP_PM_SRCSEL_GRP3__SHIFT 24 +#define NVC0_3D_MP_PM_SRCSEL_SIG3__MASK 0x70000000 +#define NVC0_3D_MP_PM_SRCSEL_SIG3__SHIFT 28 + +#define NVE4_3D_MP_PM_SRCSEL(i0) (0x0000339c + 0x4*(i0)) +#define NVE4_3D_MP_PM_SRCSEL__ESIZE 0x00000004 +#define NVE4_3D_MP_PM_SRCSEL__LEN 0x00000008 +#define NVE4_3D_MP_PM_SRCSEL_GRP0__MASK 0x00000003 +#define NVE4_3D_MP_PM_SRCSEL_GRP0__SHIFT 0 +#define NVE4_3D_MP_PM_SRCSEL_SIG0__MASK 0x0000001c +#define NVE4_3D_MP_PM_SRCSEL_SIG0__SHIFT 2 +#define NVE4_3D_MP_PM_SRCSEL_GRP1__MASK 0x00000060 +#define NVE4_3D_MP_PM_SRCSEL_GRP1__SHIFT 5 +#define NVE4_3D_MP_PM_SRCSEL_SIG1__MASK 0x00000380 +#define NVE4_3D_MP_PM_SRCSEL_SIG1__SHIFT 7 +#define NVE4_3D_MP_PM_SRCSEL_GRP2__MASK 0x00000c00 +#define NVE4_3D_MP_PM_SRCSEL_GRP2__SHIFT 10 +#define NVE4_3D_MP_PM_SRCSEL_SIG2__MASK 0x00007000 +#define NVE4_3D_MP_PM_SRCSEL_SIG2__SHIFT 12 +#define NVE4_3D_MP_PM_SRCSEL_GRP3__MASK 0x00018000 +#define NVE4_3D_MP_PM_SRCSEL_GRP3__SHIFT 15 +#define NVE4_3D_MP_PM_SRCSEL_SIG3__MASK 0x000e0000 +#define NVE4_3D_MP_PM_SRCSEL_SIG3__SHIFT 17 +#define NVE4_3D_MP_PM_SRCSEL_GRP4__MASK 0x00300000 +#define NVE4_3D_MP_PM_SRCSEL_GRP4__SHIFT 20 +#define NVE4_3D_MP_PM_SRCSEL_SIG4__MASK 0x01c00000 +#define NVE4_3D_MP_PM_SRCSEL_SIG4__SHIFT 22 +#define NVE4_3D_MP_PM_SRCSEL_GRP5__MASK 0x06000000 +#define NVE4_3D_MP_PM_SRCSEL_GRP5__SHIFT 25 +#define NVE4_3D_MP_PM_SRCSEL_SIG5__MASK 0x38000000 +#define NVE4_3D_MP_PM_SRCSEL_SIG5__SHIFT 27 + +#define NVC0_3D_MP_PM_OP(i0) (0x000033bc + 0x4*(i0)) +#define NVC0_3D_MP_PM_OP__ESIZE 0x00000004 +#define NVC0_3D_MP_PM_OP__LEN 0x00000008 +#define NVC0_3D_MP_PM_OP_MODE__MASK 0x00000001 +#define NVC0_3D_MP_PM_OP_MODE__SHIFT 0 +#define NVC0_3D_MP_PM_OP_MODE_LOGOP 0x00000000 +#define NVC0_3D_MP_PM_OP_MODE_LOGOP_PULSE 0x00000001 +#define NVC0_3D_MP_PM_OP_FUNC__MASK 0x000ffff0 +#define NVC0_3D_MP_PM_OP_FUNC__SHIFT 4 + +#define NVE4_3D_MP_PM_FUNC(i0) (0x000033bc + 0x4*(i0)) +#define NVE4_3D_MP_PM_FUNC__ESIZE 0x00000004 +#define NVE4_3D_MP_PM_FUNC__LEN 0x00000008 +#define NVE4_3D_MP_PM_FUNC_MODE__MASK 0x0000000f +#define NVE4_3D_MP_PM_FUNC_MODE__SHIFT 0 +#define NVE4_3D_MP_PM_FUNC_MODE_LOGOP 0x00000000 +#define NVE4_3D_MP_PM_FUNC_MODE_LOGOP_PULSE 0x00000001 +#define NVE4_3D_MP_PM_FUNC_MODE_B6 0x00000002 +#define NVE4_3D_MP_PM_FUNC_MODE_UNK3 0x00000003 +#define NVE4_3D_MP_PM_FUNC_MODE_LOGOP_B6 0x00000004 +#define NVE4_3D_MP_PM_FUNC_MODE_LOGOP_B6_PULSE 0x00000005 +#define NVE4_3D_MP_PM_FUNC_MODE_UNK6 0x00000006 +#define NVE4_3D_MP_PM_FUNC_MODE_UNK7 0x00000007 +#define NVE4_3D_MP_PM_FUNC_MODE_UNK8 0x00000008 +#define NVE4_3D_MP_PM_FUNC_FUNC__MASK 0x000ffff0 +#define NVE4_3D_MP_PM_FUNC_FUNC__SHIFT 4 + +#define NVC0_3D_MP_PM_UNK33DC 0x000033dc + +#define NVC0_3D_NVRM_MACRO_VERTEX_ARRAY_SELECT 0x00003820 + +#define NVC0_3D_NVRM_MACRO_BLEND_ENABLES 0x00003858 + +#define NVC0_3D_NVRM_MACRO_POLYGON_MODE_FRONT 0x00003868 +#define NVC0_3D_NVRM_MACRO_POLYGON_MODE_FRONT_POINT 0x00001b00 +#define NVC0_3D_NVRM_MACRO_POLYGON_MODE_FRONT_LINE 0x00001b01 +#define NVC0_3D_NVRM_MACRO_POLYGON_MODE_FRONT_FILL 0x00001b02 + +#define NVC0_3D_NVRM_MACRO_POLYGON_MODE_BACK 0x00003870 +#define NVC0_3D_NVRM_MACRO_POLYGON_MODE_BACK_POINT 0x00001b00 +#define NVC0_3D_NVRM_MACRO_POLYGON_MODE_BACK_LINE 0x00001b01 +#define NVC0_3D_NVRM_MACRO_POLYGON_MODE_BACK_FILL 0x00001b02 + +#define NVC0_3D_NVRM_MACRO_GP_SELECT 0x00003878 + +#define NVC0_3D_NVRM_MACRO_TEP_SELECT 0x00003880 + + +#endif /* NVC0_3D_XML */ -- 2.7.3
Ilia Mirkin
2016-Oct-27 14:02 UTC
[Nouveau] [PATCH v2 3/7] nvc0: make use of the new hwdefs for TEX_CB_INDEX
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> --- src/nvc0_accel.c | 2 +- src/nvc0_accel.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c index 52a17db..0682806 100644 --- a/src/nvc0_accel.c +++ b/src/nvc0_accel.c @@ -313,7 +313,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) PUSH_DATA (push, 0x00000001); BEGIN_NVC0(push, NVC0_3D(CB_BIND(4)), 1); PUSH_DATA (push, 0x11); - BEGIN_NVC0(push, SUBC_3D(0x2608), 1); + BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1); PUSH_DATA (push, 1); } diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h index 4c3bb0f..607e97b 100644 --- a/src/nvc0_accel.h +++ b/src/nvc0_accel.h @@ -12,6 +12,7 @@ /* subchannel assignments, compatible with kepler's fixed layout */ #define SUBC_3D(mthd) 0, (mthd) #define NVC0_3D(mthd) SUBC_3D(NVC0_3D_##mthd) +#define NVE4_3D(mthd) SUBC_3D(NVE4_3D_##mthd) #define SUBC_M2MF(mthd) 2, (mthd) #define SUBC_P2MF(mthd) 2, (mthd) #define NVC0_M2MF(mthd) SUBC_M2MF(NVC0_M2MF_##mthd) -- 2.7.3
Ilia Mirkin
2016-Oct-27 14:02 UTC
[Nouveau] [PATCH v2 4/7] nvc0: rename BEGIN_IMC0 to IMMED_NVC0
For consistency with mesa. It wasn't used anywhere previously.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
src/nouveau_local.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/nouveau_local.h b/src/nouveau_local.h
index 3de69a2..dd49395 100644
--- a/src/nouveau_local.h
+++ b/src/nouveau_local.h
@@ -237,7 +237,7 @@ BEGIN_NIC0(struct nouveau_pushbuf *push, int subc, int mthd,
int size)
}
static inline void
-BEGIN_IMC0(struct nouveau_pushbuf *push, int subc, int mthd, int data)
+IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, int data)
{
PUSH_DATA (push, 0x80000000 | (data << 16) | (subc << 13) | (mthd
/ 4));
}
--
2.7.3
Ilia Mirkin
2016-Oct-27 14:02 UTC
[Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nvc0_accel.c | 11 ++++++++++
src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 23 ++++---------------
src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 64 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use center sample locations. */
+ BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ }
}
BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 607e97b..959f67f 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -7,6 +7,7 @@
#include "hwdefs/nvc0_m2mf.xml.h"
#include "hwdefs/nv50_defs.xml.h"
#include "hwdefs/nv50_texture.h"
+#include "hwdefs/gm107_texture.xml.h"
#include "hwdefs/nv_3ddefs.xml.h"
/* subchannel assignments, compatible with kepler's fixed layout */
@@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct nouveau_bo
*bo,
}
}
+static __inline__ void
+PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned offset,
+ unsigned width, unsigned height, unsigned pitch, unsigned format)
+{
+ if (push->client->device->chipset < 0x110) {
+ unsigned tic2 = 0xd0001000;
+ if (pitch == 0)
+ tic2 |= 0x00004000;
+ else
+ tic2 |= 0x0005c000;
+ PUSH_DATA(push, format);
+ PUSH_DATA(push, bo->offset + offset);
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ (bo->config.nvc0.tile_mode << 18) |
+ tic2);
+ PUSH_DATA(push, 0x00300000);
+ PUSH_DATA(push, 0x80000000 | width);
+ PUSH_DATA(push, 0x00010000 | height);
+ PUSH_DATA(push, 0x03000000);
+ PUSH_DATA(push, 0x00000000);
+ } else {
+ unsigned tile_mode = bo->config.nvc0.tile_mode;
+ PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) << 1));
+ PUSH_DATA(push, bo->offset + offset);
+ if (pitch == 0) {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ ((tile_mode & 0x007)) |
+ ((tile_mode & 0x070) >> (4 - 3)) |
+ ((tile_mode & 0x700) >> (8 - 6)));
+ PUSH_DATA(push, GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
+ GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
+ ((height - 1) & 0xffff));
+ PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO |
+ GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
+ PUSH_DATA(push, 0x00000000);
+ } else {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_PITCH);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ (pitch >> 5));
+ PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1));
+ PUSH_DATA(push, 0x000000000);
+ PUSH_DATA(push, 0x000000000);
+ }
+ }
+}
+
#endif
diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
index a53dfe6..017a7da 100644
--- a/src/nvc0_exa.c
+++ b/src/nvc0_exa.c
@@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict, PicturePtr pdpict,
int op)
static Bool
NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit)
{
- uint64_t offset = pNv->scratch->offset + SOLID(unit);
struct nouveau_pushbuf *push = pNv->pushbuf;
PUSH_DATAu(push, pNv->scratch, SOLID(unit), 1);
PUSH_DATA (push, ppict->pSourcePict->solidFill.color);
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
- PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
- PUSH_DATA (push, offset);
- PUSH_DATA (push, (offset >> 32) | 0xd005d000);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, 0x00000001);
- PUSH_DATA (push, 0x00010001);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ PUSH_TIC (push, pNv->scratch, SOLID(unit), 1, 1, 4,
+ _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
PUSH_DATA (push, NV50TSC_1_0_WRAPS_REPEAT |
NV50TSC_1_0_WRAPT_REPEAT |
@@ -651,16 +644,8 @@ NVC0EXAPictTexture(NVPtr pNv, PixmapPtr ppix, PicturePtr
ppict, unsigned unit)
PUSH_REFN (push, bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
- PUSH_DATA (push, format);
- PUSH_DATA (push, bo->offset);
- PUSH_DATA (push, (bo->offset >> 32) |
- (bo->config.nvc0.tile_mode << 18) |
- 0xd0005000);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, (1 << 31) | ppix->drawable.width);
- PUSH_DATA (push, (1 << 16) | ppix->drawable.height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ PUSH_TIC (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0,
+ format);
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
if (ppict->repeat) {
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index 129c505..c3e58da 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
};
struct nouveau_pushbuf *push = pNv->pushbuf;
- uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
float X1, X2, Y1, Y2;
BoxPtr pbox;
int nbox;
@@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
if (id == FOURCC_YV12 || id == FOURCC_I420) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
+ PUSH_TIC(push, src, packed_y, width, height, 0,
+ NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_FMT_8);
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
+ PUSH_TIC(push, src, uv, width >> 1, height >> 1, 0,
+ NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_FMT_8_8);
- PUSH_DATA (push, ((src->offset + uv)));
- PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width >> 1);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
} else {
- if (id == FOURCC_UYVY) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
+ unsigned format;
+ if (id == FOURCC_UYVY) {
+ format = NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8);
- } else {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8;
+ } else {
+ format = NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8);
- }
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
- if (id == FOURCC_UYVY) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8;
+ }
+ PUSH_TIC(push, src, packed_y, width, height, 0, format);
+
+ if (id == FOURCC_UYVY) {
+ format = NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8_8_8);
- } else {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8_8_8;
+ } else {
+ format = NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C1 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8_8_8);
- }
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, (width >> 1));
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ NV50TIC_0_0_FMT_8_8_8_8;
+ }
+ PUSH_TIC(push, src, packed_y, width >> 1, height, 0, format);
}
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET, 16);
--
2.7.3
Ilia Mirkin
2016-Oct-27 14:02 UTC
[Nouveau] [PATCH v2 6/7] copy: add maxwell/pascal copy engine classes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nouveau_copy.c | 2 ++
src/nvc0_accel.c | 10 +++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
index c139de6..7118a7a 100644
--- a/src/nouveau_copy.c
+++ b/src/nouveau_copy.c
@@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen)
int engine;
Bool (*init)(NVPtr);
} methods[] = {
+ { 0xc0b5, 0, nouveau_copya0b5_init },
+ { 0xb0b5, 0, nouveau_copya0b5_init },
{ 0xa0b5, 0, nouveau_copya0b5_init },
{ 0x90b8, 5, nouveau_copy90b5_init },
{ 0x90b5, 4, nouveau_copy90b5_init },
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 8da5051..d0a835e 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -156,9 +156,17 @@ NVAccelInitCOPY_NVE0(ScrnInfoPtr pScrn)
{
NVPtr pNv = NVPTR(pScrn);
struct nouveau_pushbuf *push = pNv->pushbuf;
+ uint32_t class;
int ret;
- ret = nouveau_object_new(pNv->channel, 0x0000a0b5, 0xa0b5,
+ if (pNv->dev->chipset < 0x110)
+ class = 0xa0b5;
+ else if (pNv->dev->chipset < 0x130)
+ class = 0xb0b5;
+ else
+ class = 0xc0b5;
+
+ ret = nouveau_object_new(pNv->channel, class, class,
NULL, 0, &pNv->NvCOPY);
if (ret)
return FALSE;
--
2.7.3
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nv_driver.c | 2 ++
src/nvc0_accel.c | 10 +++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/nv_driver.c b/src/nv_driver.c
index fff83f8..61940a8 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -390,6 +390,7 @@ NVHasKMS(struct pci_device *pci_dev, struct
xf86_platform_device *platform_dev)
case 0xf0:
case 0x100:
case 0x110:
+ case 0x120:
break;
default:
xf86DrvMsg(-1, X_ERROR, "Unknown chipset: NV%02X\n", chipset);
@@ -941,6 +942,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
pNv->Architecture = NV_KEPLER;
break;
case 0x110:
+ case 0x120:
pNv->Architecture = NV_MAXWELL;
break;
default:
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index d0a835e..6c2bae8 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -244,9 +244,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
} else if (pNv->dev->chipset < 0x110) {
class = 0xa197;
handle = 0x0000906e;
- } else {
+ } else if (pNv->dev->chipset < 0x120) {
class = 0xb097;
handle = 0x0000906e;
+ } else if (pNv->dev->chipset < 0x130) {
+ class = 0xb197;
+ handle = 0x0000906e;
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "No 3D acceleration support for NV%X\n",
+ pNv->dev->chipset);
+ return FALSE;
}
ret = nouveau_object_new(pNv->channel, class, class,
--
2.7.3
Samuel Pitoiset
2016-Oct-27 17:10 UTC
[Nouveau] [PATCH v2 6/7] copy: add maxwell/pascal copy engine classes
0xc0b5 is not in rnndb, I guess it should be GP100_COPY, right? Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> On 10/27/2016 04:02 PM, Ilia Mirkin wrote:> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nouveau_copy.c | 2 ++ > src/nvc0_accel.c | 10 +++++++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c > index c139de6..7118a7a 100644 > --- a/src/nouveau_copy.c > +++ b/src/nouveau_copy.c > @@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen) > int engine; > Bool (*init)(NVPtr); > } methods[] = { > + { 0xc0b5, 0, nouveau_copya0b5_init }, > + { 0xb0b5, 0, nouveau_copya0b5_init }, > { 0xa0b5, 0, nouveau_copya0b5_init }, > { 0x90b8, 5, nouveau_copy90b5_init }, > { 0x90b5, 4, nouveau_copy90b5_init }, > diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c > index 8da5051..d0a835e 100644 > --- a/src/nvc0_accel.c > +++ b/src/nvc0_accel.c > @@ -156,9 +156,17 @@ NVAccelInitCOPY_NVE0(ScrnInfoPtr pScrn) > { > NVPtr pNv = NVPTR(pScrn); > struct nouveau_pushbuf *push = pNv->pushbuf; > + uint32_t class; > int ret; > > - ret = nouveau_object_new(pNv->channel, 0x0000a0b5, 0xa0b5, > + if (pNv->dev->chipset < 0x110) > + class = 0xa0b5; > + else if (pNv->dev->chipset < 0x130) > + class = 0xb0b5; > + else > + class = 0xc0b5; > + > + ret = nouveau_object_new(pNv->channel, class, class, > NULL, 0, &pNv->NvCOPY); > if (ret) > return FALSE; >
Samuel Pitoiset
2016-Oct-27 17:11 UTC
[Nouveau] [PATCH v2 7/7] recognize and accelerate GM20x
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> On 10/27/2016 04:03 PM, Ilia Mirkin wrote:> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nv_driver.c | 2 ++ > src/nvc0_accel.c | 10 +++++++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/src/nv_driver.c b/src/nv_driver.c > index fff83f8..61940a8 100644 > --- a/src/nv_driver.c > +++ b/src/nv_driver.c > @@ -390,6 +390,7 @@ NVHasKMS(struct pci_device *pci_dev, struct xf86_platform_device *platform_dev) > case 0xf0: > case 0x100: > case 0x110: > + case 0x120: > break; > default: > xf86DrvMsg(-1, X_ERROR, "Unknown chipset: NV%02X\n", chipset); > @@ -941,6 +942,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags) > pNv->Architecture = NV_KEPLER; > break; > case 0x110: > + case 0x120: > pNv->Architecture = NV_MAXWELL; > break; > default: > diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c > index d0a835e..6c2bae8 100644 > --- a/src/nvc0_accel.c > +++ b/src/nvc0_accel.c > @@ -244,9 +244,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) > } else if (pNv->dev->chipset < 0x110) { > class = 0xa197; > handle = 0x0000906e; > - } else { > + } else if (pNv->dev->chipset < 0x120) { > class = 0xb097; > handle = 0x0000906e; > + } else if (pNv->dev->chipset < 0x130) { > + class = 0xb197; > + handle = 0x0000906e; > + } else { > + xf86DrvMsg(pScrn->scrnIndex, X_INFO, > + "No 3D acceleration support for NV%X\n", > + pNv->dev->chipset); > + return FALSE; > } > > ret = nouveau_object_new(pNv->channel, class, class, >
Samuel Pitoiset
2016-Oct-27 17:19 UTC
[Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
Are you sure this refactoring doesn't break anything? Few comments inline. On 10/27/2016 04:02 PM, Ilia Mirkin wrote:> This flips GM10x to using the updated format, which is what I tested > with. However GM20x and GP10x also use this TIC format. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nvc0_accel.c | 11 ++++++++++ > src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++ > src/nvc0_exa.c | 23 ++++--------------- > src/nvc0_xv.c | 67 +++++++++++++++++++------------------------------------- > 4 files changed, 93 insertions(+), 64 deletions(-) > > diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c > index 0682806..8da5051 100644 > --- a/src/nvc0_accel.c > +++ b/src/nvc0_accel.c > @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) > PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); > PUSH_DATA (push, (bo->offset + MISC_OFFSET)); > PUSH_DATA (push, 1); > + } else { > + /* Use new TIC format. Not strictly necessary for GM20x+ */ > + IMMED_NVC0(push, SUBC_3D(0x0f10), 1); > + if (pNv->dev->chipset >= 0x120) { > + /* Use center sample locations. */ > + BEGIN_NVC0(push, SUBC_3D(0x11e0), 4); > + PUSH_DATA (push, 0x88888888); > + PUSH_DATA (push, 0x88888888); > + PUSH_DATA (push, 0x88888888); > + PUSH_DATA (push, 0x88888888); > + } > } > > BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2); > diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h > index 607e97b..959f67f 100644 > --- a/src/nvc0_accel.h > +++ b/src/nvc0_accel.h > @@ -7,6 +7,7 @@ > #include "hwdefs/nvc0_m2mf.xml.h" > #include "hwdefs/nv50_defs.xml.h" > #include "hwdefs/nv50_texture.h" > +#include "hwdefs/gm107_texture.xml.h" > #include "hwdefs/nv_3ddefs.xml.h" > > /* subchannel assignments, compatible with kepler's fixed layout */ > @@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct nouveau_bo *bo, > } > } > > +static __inline__ void > +PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned offset, > + unsigned width, unsigned height, unsigned pitch, unsigned format) > +{ > + if (push->client->device->chipset < 0x110) { > + unsigned tic2 = 0xd0001000; > + if (pitch == 0) > + tic2 |= 0x00004000; > + else > + tic2 |= 0x0005c000; > + PUSH_DATA(push, format); > + PUSH_DATA(push, bo->offset + offset); > + PUSH_DATA(push, ((bo->offset + offset) >> 32) | > + (bo->config.nvc0.tile_mode << 18) | > + tic2); > + PUSH_DATA(push, 0x00300000); > + PUSH_DATA(push, 0x80000000 | width); > + PUSH_DATA(push, 0x00010000 | height); > + PUSH_DATA(push, 0x03000000); > + PUSH_DATA(push, 0x00000000); > + } else { > + unsigned tile_mode = bo->config.nvc0.tile_mode; > + PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) << 1)); > + PUSH_DATA(push, bo->offset + offset); > + if (pitch == 0) { > + PUSH_DATA(push, ((bo->offset + offset) >> 32) | > + GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR); > + PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 | > + ((tile_mode & 0x007)) | > + ((tile_mode & 0x070) >> (4 - 3)) | > + ((tile_mode & 0x700) >> (8 - 6))); > + PUSH_DATA(push, GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V | > + GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR | > + GM107_TIC2_4_TEXTURE_TYPE_TWO_D | > + (width - 1)); > + PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | > + ((height - 1) & 0xffff)); > + PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO | > + GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE); > + PUSH_DATA(push, 0x00000000); > + } else { > + PUSH_DATA(push, ((bo->offset + offset) >> 32) | > + GM107_TIC2_2_HEADER_VERSION_PITCH); > + PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 | > + (pitch >> 5)); > + PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR | > + GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP | > + (width - 1)); > + PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1)); > + PUSH_DATA(push, 0x000000000); > + PUSH_DATA(push, 0x000000000); > + } > + } > +} > + > #endif > diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c > index a53dfe6..017a7da 100644 > --- a/src/nvc0_exa.c > +++ b/src/nvc0_exa.c > @@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict, PicturePtr pdpict, int op) > static Bool > NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit) > { > - uint64_t offset = pNv->scratch->offset + SOLID(unit); > struct nouveau_pushbuf *push = pNv->pushbuf; > > PUSH_DATAu(push, pNv->scratch, SOLID(unit), 1); > PUSH_DATA (push, ppict->pSourcePict->solidFill.color); > PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8); > - PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8)); > - PUSH_DATA (push, offset); > - PUSH_DATA (push, (offset >> 32) | 0xd005d000); > - PUSH_DATA (push, 0x00300000); > - PUSH_DATA (push, 0x00000001);You always set bit-31 in PUSH_TIC, but it's not set here, is that intended?> - PUSH_DATA (push, 0x00010001); > - PUSH_DATA (push, 0x03000000); > - PUSH_DATA (push, 0x00000000); > + PUSH_TIC (push, pNv->scratch, SOLID(unit), 1, 1, 4, > + _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8)); > PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8); > PUSH_DATA (push, NV50TSC_1_0_WRAPS_REPEAT | > NV50TSC_1_0_WRAPT_REPEAT | > @@ -651,16 +644,8 @@ NVC0EXAPictTexture(NVPtr pNv, PixmapPtr ppix, PicturePtr ppict, unsigned unit) > > PUSH_REFN (push, bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); > PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8); > - PUSH_DATA (push, format); > - PUSH_DATA (push, bo->offset); > - PUSH_DATA (push, (bo->offset >> 32) | > - (bo->config.nvc0.tile_mode << 18) | > - 0xd0005000); > - PUSH_DATA (push, 0x00300000); > - PUSH_DATA (push, (1 << 31) | ppix->drawable.width); > - PUSH_DATA (push, (1 << 16) | ppix->drawable.height); > - PUSH_DATA (push, 0x03000000); > - PUSH_DATA (push, 0x00000000); > + PUSH_TIC (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0, > + format); > > PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8); > if (ppict->repeat) { > diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c > index 129c505..c3e58da 100644 > --- a/src/nvc0_xv.c > +++ b/src/nvc0_xv.c > @@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn, > { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR }, > }; > struct nouveau_pushbuf *push = pNv->pushbuf; > - uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18); > float X1, X2, Y1, Y2; > BoxPtr pbox; > int nbox; > @@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn, > > PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16); > if (id == FOURCC_YV12 || id == FOURCC_I420) { > - PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM | > + PUSH_TIC(push, src, packed_y, width, height, 0, > + NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM | > NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM | > NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM | > NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM | > NV50TIC_0_0_FMT_8); > - PUSH_DATA (push, ((src->offset + packed_y))); > - PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode); > - PUSH_DATA (push, 0x00300000); > - PUSH_DATA (push, width);Same here, I bet bit-31 is not set. :-)> - PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height); > - PUSH_DATA (push, 0x03000000); > - PUSH_DATA (push, 0x00000000); > - PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM | > + PUSH_TIC(push, src, uv, width >> 1, height >> 1, 0, > + NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM | > NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM | > NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM | > NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM | > NV50TIC_0_0_FMT_8_8); > - PUSH_DATA (push, ((src->offset + uv))); > - PUSH_DATA (push, ((src->offset + uv) >> 32) | mode); > - PUSH_DATA (push, 0x00300000); > - PUSH_DATA (push, width >> 1); > - PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1)); > - PUSH_DATA (push, 0x03000000); > - PUSH_DATA (push, 0x00000000); > } else { > - if (id == FOURCC_UYVY) { > - PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM | > + unsigned format; > + if (id == FOURCC_UYVY) { > + format = NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM | > NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM | > NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM | > NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM | > - NV50TIC_0_0_FMT_8_8); > - } else { > - PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM | > + NV50TIC_0_0_FMT_8_8; > + } else { > + format = NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM | > NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM | > NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM | > NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM | > - NV50TIC_0_0_FMT_8_8); > - } > - PUSH_DATA (push, ((src->offset + packed_y))); > - PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode); > - PUSH_DATA (push, 0x00300000); > - PUSH_DATA (push, width); > - PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height); > - PUSH_DATA (push, 0x03000000); > - PUSH_DATA (push, 0x00000000); > - if (id == FOURCC_UYVY) { > - PUSH_DATA (push, NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM | > + NV50TIC_0_0_FMT_8_8; > + } > + PUSH_TIC(push, src, packed_y, width, height, 0, format); > + > + if (id == FOURCC_UYVY) { > + format = NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM | > NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM | > NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM | > NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM | > - NV50TIC_0_0_FMT_8_8_8_8); > - } else { > - PUSH_DATA (push, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM | > + NV50TIC_0_0_FMT_8_8_8_8; > + } else { > + format = NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM | > NV50TIC_0_0_MAPB_C1 | NV50TIC_0_0_TYPEB_UNORM | > NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM | > NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM | > - NV50TIC_0_0_FMT_8_8_8_8); > - } > - PUSH_DATA (push, ((src->offset + packed_y))); > - PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode); > - PUSH_DATA (push, 0x00300000); > - PUSH_DATA (push, (width >> 1)); > - PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height); > - PUSH_DATA (push, 0x03000000); > - PUSH_DATA (push, 0x00000000); > + NV50TIC_0_0_FMT_8_8_8_8; > + } > + PUSH_TIC(push, src, packed_y, width >> 1, height, 0, format); > } > > PUSH_DATAu(push, pNv->scratch, TSC_OFFSET, 16); >
Samuel Pitoiset
2016-Oct-27 17:37 UTC
[Nouveau] [PATCH v2 1/7] exa: add GM10x acceleration support
Two minor nitpicks below. I didn't read all shaders carefully because it's a pain, but I didn't see any obvious things. :-) Thanks for that great work Ilia! Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> On 10/27/2016 04:02 PM, Ilia Mirkin wrote:> rendercheck -f a8r8g8b8 passes as much as on a GK208, and xv appears to > work. Very lightly tested. > > Instead of sticking coordinates into pushbufs, the vertex shader is > modified to read them from a constbuf, indexed by vertex id. This > approach could be used for all nvc0 generations, but I didn't want to > rock the boat. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/Makefile.am | 16 ++++++++ > src/nouveau_copy.c | 1 + > src/nouveau_exa.c | 2 +- > src/nouveau_xv.c | 2 +- > src/nv_accel_common.c | 1 + > src/nv_driver.c | 1 + > src/nvc0_accel.c | 37 ++++++++++++++--- > src/nvc0_exa.c | 48 ++++++++++++++++++++-- > src/nvc0_xv.c | 48 ++++++++++++++++++++-- > src/shader/Makefile | 23 ++++++++--- > src/shader/exac8nv110.fp | 47 +++++++++++++++++++++ > src/shader/exac8nv110.fpc | 38 +++++++++++++++++ > src/shader/exacanv110.fp | 47 +++++++++++++++++++++ > src/shader/exacanv110.fpc | 38 +++++++++++++++++ > src/shader/exacmnv110.fp | 47 +++++++++++++++++++++ > src/shader/exacmnv110.fpc | 38 +++++++++++++++++ > src/shader/exas8nv110.fp | 42 +++++++++++++++++++ > src/shader/exas8nv110.fpc | 28 +++++++++++++ > src/shader/exasanv110.fp | 47 +++++++++++++++++++++ > src/shader/exasanv110.fpc | 38 +++++++++++++++++ > src/shader/exascnv110.fp | 38 +++++++++++++++++ > src/shader/exascnv110.fpc | 20 +++++++++ > src/shader/videonv110.fp | 54 ++++++++++++++++++++++++ > src/shader/videonv110.fpc | 52 +++++++++++++++++++++++ > src/shader/xfrm2nv110.vp | 82 +++++++++++++++++++++++++++++++++++++ > src/shader/xfrm2nv110.vpc | 102 ++++++++++++++++++++++++++++++++++++++++++++++ > 26 files changed, 918 insertions(+), 19 deletions(-) > create mode 100644 src/shader/exac8nv110.fp > create mode 100644 src/shader/exac8nv110.fpc > create mode 100644 src/shader/exacanv110.fp > create mode 100644 src/shader/exacanv110.fpc > create mode 100644 src/shader/exacmnv110.fp > create mode 100644 src/shader/exacmnv110.fpc > create mode 100644 src/shader/exas8nv110.fp > create mode 100644 src/shader/exas8nv110.fpc > create mode 100644 src/shader/exasanv110.fp > create mode 100644 src/shader/exasanv110.fpc > create mode 100644 src/shader/exascnv110.fp > create mode 100644 src/shader/exascnv110.fpc > create mode 100644 src/shader/videonv110.fp > create mode 100644 src/shader/videonv110.fpc > create mode 100644 src/shader/xfrm2nv110.vp > create mode 100644 src/shader/xfrm2nv110.vpc > > diff --git a/src/Makefile.am b/src/Makefile.am > index 1e04ddf..6ba8d87 100644 > --- a/src/Makefile.am > +++ b/src/Makefile.am > @@ -77,48 +77,64 @@ EXTRA_DIST = hwdefs/nv_3ddefs.xml.h \ > shader/exac8nve0.fpc \ > shader/exac8nvf0.fp \ > shader/exac8nvf0.fpc \ > + shader/exac8nv110.fp \ > + shader/exac8nv110.fpc \ > shader/exacanvc0.fp \ > shader/exacanvc0.fpc \ > shader/exacanve0.fp \ > shader/exacanve0.fpc \ > shader/exacanvf0.fp \ > shader/exacanvf0.fpc \ > + shader/exacanv110.fp \ > + shader/exacanv110.fpc \ > shader/exacmnvc0.fp \ > shader/exacmnvc0.fpc \ > shader/exacmnve0.fp \ > shader/exacmnve0.fpc \ > shader/exacmnvf0.fp \ > shader/exacmnvf0.fpc \ > + shader/exacmnv110.fp \ > + shader/exacmnv110.fpc \ > shader/exas8nvc0.fp \ > shader/exas8nvc0.fpc \ > shader/exas8nve0.fp \ > shader/exas8nve0.fpc \ > shader/exas8nvf0.fp \ > shader/exas8nvf0.fpc \ > + shader/exas8nv110.fp \ > + shader/exas8nv110.fpc \ > shader/exasanvc0.fp \ > shader/exasanvc0.fpc \ > shader/exasanve0.fp \ > shader/exasanve0.fpc \ > shader/exasanvf0.fp \ > shader/exasanvf0.fpc \ > + shader/exasanv110.fp \ > + shader/exasanv110.fpc \ > shader/exascnvc0.fp \ > shader/exascnvc0.fpc \ > shader/exascnve0.fp \ > shader/exascnve0.fpc \ > shader/exascnvf0.fp \ > shader/exascnvf0.fpc \ > + shader/exascnv110.fp \ > + shader/exascnv110.fpc \ > shader/videonvc0.fp \ > shader/videonvc0.fpc \ > shader/videonve0.fp \ > shader/videonve0.fpc \ > shader/videonvf0.fp \ > shader/videonvf0.fpc \ > + shader/videonv110.fp \ > + shader/videonv110.fpc \ > shader/xfrm2nvc0.vp \ > shader/xfrm2nvc0.vpc \ > shader/xfrm2nve0.vp \ > shader/xfrm2nve0.vpc \ > shader/xfrm2nvf0.vp \ > shader/xfrm2nvf0.vpc \ > + shader/xfrm2nv110.vp \ > + shader/xfrm2nv110.vpc \ > shader/Makefile \ > nouveau_local.h \ > nouveau_copy.h \ > diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c > index e152a53..c139de6 100644 > --- a/src/nouveau_copy.c > +++ b/src/nouveau_copy.c > @@ -81,6 +81,7 @@ nouveau_copy_init(ScreenPtr pScreen) > &pNv->ce_channel); > break; > case NV_KEPLER: > + case NV_MAXWELL: > ret = nouveau_object_new(&pNv->dev->object, 0, > NOUVEAU_FIFO_CHANNEL_CLASS, > &(struct nve0_fifo) { > diff --git a/src/nouveau_exa.c b/src/nouveau_exa.c > index def66ac..0f02b99 100644 > --- a/src/nouveau_exa.c > +++ b/src/nouveau_exa.c > @@ -514,12 +514,12 @@ nouveau_exa_init(ScreenPtr pScreen) > break; > case NV_FERMI: > case NV_KEPLER: > + case NV_MAXWELL: > exa->CheckComposite = NVC0EXACheckComposite; > exa->PrepareComposite = NVC0EXAPrepareComposite; > exa->Composite = NVC0EXAComposite; > exa->DoneComposite = NVC0EXADoneComposite; > break; > - case NV_MAXWELL: > default: > break; > } > diff --git a/src/nouveau_xv.c b/src/nouveau_xv.c > index d514dbf..716b18d 100644 > --- a/src/nouveau_xv.c > +++ b/src/nouveau_xv.c > @@ -2142,7 +2142,7 @@ NVSetupTexturedVideo (ScreenPtr pScreen, XF86VideoAdaptorPtr *textureAdaptor) > textureAdaptor[0] = NV40SetupTexturedVideo(pScreen, FALSE); > textureAdaptor[1] = NV40SetupTexturedVideo(pScreen, TRUE); > } else > - if (pNv->Architecture >= NV_TESLA && pNv->Architecture < NV_MAXWELL) { > + if (pNv->Architecture >= NV_TESLA) { > textureAdaptor[0] = NV50SetupTexturedVideo(pScreen); > } > } > diff --git a/src/nv_accel_common.c b/src/nv_accel_common.c > index 9361ce8..5d12dd8 100644 > --- a/src/nv_accel_common.c > +++ b/src/nv_accel_common.c > @@ -722,6 +722,7 @@ NVAccelCommonInit(ScrnInfoPtr pScrn) > switch (pNv->Architecture) { > case NV_FERMI: > case NV_KEPLER: > + case NV_MAXWELL: > INIT_CONTEXT_OBJECT(3D_NVC0); > break; > case NV_TESLA: > diff --git a/src/nv_driver.c b/src/nv_driver.c > index 4dde8e0..fff83f8 100644 > --- a/src/nv_driver.c > +++ b/src/nv_driver.c > @@ -389,6 +389,7 @@ NVHasKMS(struct pci_device *pci_dev, struct xf86_platform_device *platform_dev) > case 0xe0: > case 0xf0: > case 0x100: > + case 0x110: > break; > default: > xf86DrvMsg(-1, X_ERROR, "Unknown chipset: NV%02X\n", chipset); > diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c > index d2a3b93..52a17db 100644 > --- a/src/nvc0_accel.c > +++ b/src/nvc0_accel.c > @@ -53,6 +53,16 @@ > #include "shader/exas8nvf0.fp" > #include "shader/exac8nvf0.fp" > > +#include "shader/xfrm2nv110.vp" > +#include "shader/videonv110.fp" > + > +#include "shader/exascnv110.fp" > +#include "shader/exacmnv110.fp" > +#include "shader/exacanv110.fp" > +#include "shader/exasanv110.fp" > +#include "shader/exas8nv110.fp" > +#include "shader/exac8nv110.fp" > + > #define NVC0PushProgram(pNv,addr,code) do { \ > const unsigned size = sizeof(code) / sizeof(code[0]); \ > PUSH_DATAu((pNv)->pushbuf, (pNv)->scratch, (addr), size); \ > @@ -223,9 +233,12 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) > } else if (pNv->dev->chipset < 0xf0) { > class = 0xa097; > handle = 0x0000906e; > - } else { > + } else if (pNv->dev->chipset < 0x110) { > class = 0xa197; > handle = 0x0000906e; > + } else { > + class = 0xb097; > + handle = 0x0000906e; > } > > ret = nouveau_object_new(pNv->channel, class, class, > @@ -304,10 +317,12 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) > PUSH_DATA (push, 1); > } > > - BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3); > - PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); > - PUSH_DATA (push, (bo->offset + MISC_OFFSET)); > - PUSH_DATA (push, 1); > + if (pNv->Architecture < NV_MAXWELL) { > + BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3); > + PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32); > + PUSH_DATA (push, (bo->offset + MISC_OFFSET)); > + PUSH_DATA (push, 1); > + } > > BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2); > PUSH_DATA (push, (bo->offset + CODE_OFFSET) >> 32); > @@ -334,7 +349,8 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) > NVC0PushProgram(pNv, PFP_S_A8, NVE0FP_Source_A8); > NVC0PushProgram(pNv, PFP_C_A8, NVE0FP_Composite_A8); > NVC0PushProgram(pNv, PFP_NV12, NVE0FP_NV12); > - } else { > + } else > + if (pNv->dev->chipset < 0x110) { > NVC0PushProgram(pNv, PVP_PASS, NVF0VP_Transform2); > NVC0PushProgram(pNv, PFP_S, NVF0FP_Source); > NVC0PushProgram(pNv, PFP_C, NVF0FP_Composite); > @@ -343,6 +359,15 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) > NVC0PushProgram(pNv, PFP_S_A8, NVF0FP_Source_A8); > NVC0PushProgram(pNv, PFP_C_A8, NVF0FP_Composite_A8); > NVC0PushProgram(pNv, PFP_NV12, NVF0FP_NV12); > + } else { > + NVC0PushProgram(pNv, PVP_PASS, NV110VP_Transform2); > + NVC0PushProgram(pNv, PFP_S, NV110FP_Source); > + NVC0PushProgram(pNv, PFP_C, NV110FP_Composite); > + NVC0PushProgram(pNv, PFP_CCA, NV110FP_CAComposite); > + NVC0PushProgram(pNv, PFP_CCASA, NV110FP_CACompositeSrcAlpha); > + NVC0PushProgram(pNv, PFP_S_A8, NV110FP_Source_A8); > + NVC0PushProgram(pNv, PFP_C_A8, NV110FP_Composite_A8); > + NVC0PushProgram(pNv, PFP_NV12, NV110FP_NV12); > } > > BEGIN_NVC0(push, NVC0_3D(SP_SELECT(1)), 4); > diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c > index 6add60b..a53dfe6 100644 > --- a/src/nvc0_exa.c > +++ b/src/nvc0_exa.c > @@ -914,14 +914,56 @@ NVC0EXAComposite(PixmapPtr pdpix, > if (!PUSH_SPACE(push, 64)) > return; > > + if (pNv->dev->chipset >= 0x110) { > + BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); > + PUSH_DATA (push, 256); > + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA) >> 32); > + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA)); > + BEGIN_1IC0(push, NVC0_3D(CB_POS), 3 * (4 + 2 + 2) + 1);I would suggest only "1 + 24" here, but your call.> + PUSH_DATA (push, 0x80); > + > + PUSH_DATAf(push, dx); > + PUSH_DATAf(push, dy + (h * 2)); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 1); > + PUSH_DATAf(push, sx); > + PUSH_DATAf(push, sy + (h * 2)); > + PUSH_DATAf(push, mx); > + PUSH_DATAf(push, my + (h * 2)); > + > + PUSH_DATAf(push, dx); > + PUSH_DATAf(push, dy); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 1); > + PUSH_DATAf(push, sx); > + PUSH_DATAf(push, sy); > + PUSH_DATAf(push, mx); > + PUSH_DATAf(push, my); > + > + PUSH_DATAf(push, dx + (w * 2)); > + PUSH_DATAf(push, dy); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 1); > + PUSH_DATAf(push, sx + (w * 2)); > + PUSH_DATAf(push, sy); > + PUSH_DATAf(push, mx + (w * 2)); > + PUSH_DATAf(push, my); > + } > + > BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2); > PUSH_DATA (push, ((dx + w) << 16) | dx); > PUSH_DATA (push, ((dy + h) << 16) | dy); > BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1); > PUSH_DATA (push, NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES); > - PUSH_VTX2s(push, sx, sy + (h * 2), mx, my + (h * 2), dx, dy + (h * 2)); > - PUSH_VTX2s(push, sx, sy, mx, my, dx, dy); > - PUSH_VTX2s(push, sx + (w * 2), sy, mx + (w * 2), my, dx + (w * 2), dy); > + if (pNv->dev->chipset < 0x110) { > + PUSH_VTX2s(push, sx, sy + (h * 2), mx, my + (h * 2), dx, dy + (h * 2)); > + PUSH_VTX2s(push, sx, sy, mx, my, dx, dy); > + PUSH_VTX2s(push, sx + (w * 2), sy, mx + (w * 2), my, dx + (w * 2), dy); > + } else { > + BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2); > + PUSH_DATA (push, 0); > + PUSH_DATA (push, 3); > + } > BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 1); > PUSH_DATA (push, 0); > } > diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c > index d1d8f18..129c505 100644 > --- a/src/nvc0_xv.c > +++ b/src/nvc0_xv.c > @@ -247,15 +247,57 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn, > nouveau_pushbuf_refn (push, refs, 3)) > return BadImplementation; > > + if (pNv->dev->chipset >= 0x110) { > + BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); > + PUSH_DATA (push, 256); > + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA) >> 32); > + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA)); > + BEGIN_1IC0(push, NVC0_3D(CB_POS), 3 * (4 + 2 + 2) + 1);And here as well.> + PUSH_DATA (push, 0x80); > + > + PUSH_DATAf(push, sx1); > + PUSH_DATAf(push, sy1); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 1); > + PUSH_DATAf(push, tx1); > + PUSH_DATAf(push, ty1); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 0); > + > + PUSH_DATAf(push, sx2+(sx2-sx1)); > + PUSH_DATAf(push, sy1); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 1); > + PUSH_DATAf(push, tx2+(tx2-tx1)); > + PUSH_DATAf(push, ty1); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 0); > + > + PUSH_DATAf(push, sx1); > + PUSH_DATAf(push, sy2+(sy2-sy1)); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 1); > + PUSH_DATAf(push, tx1); > + PUSH_DATAf(push, ty2+(ty2-ty1)); > + PUSH_DATAf(push, 0); > + PUSH_DATAf(push, 0); > + } > + > BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2); > PUSH_DATA (push, sx2 << NVC0_3D_SCISSOR_HORIZ_MAX__SHIFT | sx1); > PUSH_DATA (push, sy2 << NVC0_3D_SCISSOR_VERT_MAX__SHIFT | sy1 ); > > BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1); > PUSH_DATA (push, NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES); > - PUSH_VTX1s(push, tx1, ty1, sx1, sy1); > - PUSH_VTX1s(push, tx2+(tx2-tx1), ty1, sx2+(sx2-sx1), sy1); > - PUSH_VTX1s(push, tx1, ty2+(ty2-ty1), sx1, sy2+(sy2-sy1)); > + if (pNv->dev->chipset < 0x110) { > + PUSH_VTX1s(push, tx1, ty1, sx1, sy1); > + PUSH_VTX1s(push, tx2+(tx2-tx1), ty1, sx2+(sx2-sx1), sy1); > + PUSH_VTX1s(push, tx1, ty2+(ty2-ty1), sx1, sy2+(sy2-sy1)); > + } else { > + BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2); > + PUSH_DATA (push, 0); > + PUSH_DATA (push, 3); > + } > BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 1); > PUSH_DATA (push, 0); > > diff --git a/src/shader/Makefile b/src/shader/Makefile > index 2d789be..12bf455 100644 > --- a/src/shader/Makefile > +++ b/src/shader/Makefile > @@ -22,23 +22,36 @@ NVF0_SHADERS = xfrm2nvf0.vpc \ > exas8nvf0.fpc \ > exac8nvf0.fpc \ > videonvf0.fpc > +NV110_SHADERS = xfrm2nv110.vpc \ > + exascnv110.fpc \ > + exacmnv110.fpc \ > + exacanv110.fpc \ > + exasanv110.fpc \ > + exas8nv110.fpc \ > + exac8nv110.fpc \ > + videonv110.fpc > > -SHADERS = $(NVC0_SHADERS) $(NVE0_SHADERS) $(NVF0_SHADERS) > +SHADERS = $(NVC0_SHADERS) $(NVE0_SHADERS) $(NVF0_SHADERS) $(NV110_SHADERS) > ENVYAS ?= envyas > > all: $(SHADERS) > > $(filter %nvc0.vpc,$(SHADERS)): %.vpc: %.vp > - cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -o $@ > + cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gf100 -V gf100 -o $@ > $(filter %nvc0.fpc,$(SHADERS)): %.fpc: %.fp > - cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -o $@ > + cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gf100 -V gf100 -o $@ > > $(filter %nve0.vpc,$(SHADERS)): %.vpc: %.vp > - cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -V nve4 -o $@ > + cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gf100 -V gk104 -o $@ > $(filter %nve0.fpc,$(SHADERS)): %.fpc: %.fp > - cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -V nve4 -o $@ > + cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gf100 -V gk104 -o $@ > > $(filter %nvf0.vpc,$(SHADERS)): %.vpc: %.vp > cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gk110 -o $@ > $(filter %nvf0.fpc,$(SHADERS)): %.fpc: %.fp > cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gk110 -o $@ > + > +$(filter %nv110.vpc,$(SHADERS)): %.vpc: %.vp > + cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gm107 -o $@ > +$(filter %nv110.fpc,$(SHADERS)): %.fpc: %.fp > + cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m gm107 -o $@ > diff --git a/src/shader/exac8nv110.fp b/src/shader/exac8nv110.fp > new file mode 100644 > index 0000000..ce78036 > --- /dev/null > +++ b/src/shader/exac8nv110.fp > @@ -0,0 +1,47 @@ > +#ifndef ENVYAS > +static uint32_t > +NV110FP_Composite_A8[] = { > + 0x00001462, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x80000000, > + 0x00000a0a, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x0000000f, > + 0x00000000, > +#include "exac8nv110.fpc" > +}; > +#else > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > +mufu rcp $r0 $r0 > +ipa $r3 a[0x94] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r2 a[0x90] $r0 0x0 0x1 > +tex nodep $r1 $r2 0x0 0x1 t2d 0x8 > +ipa $r3 a[0x84] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r2 a[0x80] $r0 0x0 0x1 > +tex nodep $r0 $r2 0x0 0x0 t2d 0x8 > +depbar le 0x5 0x0 0x0 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r3 $r0 $r1 > +mov $r2 $r3 0xf > +mov $r1 $r3 0xf > +sched (st 0x0) (st 0x0) (st 0x0) > +mov $r0 $r3 0xf > +exit > +#endif > diff --git a/src/shader/exac8nv110.fpc b/src/shader/exac8nv110.fpc > new file mode 100644 > index 0000000..4aa1368 > --- /dev/null > +++ b/src/shader/exac8nv110.fpc > @@ -0,0 +1,38 @@ > +0xfc0007e0, > +0x001f8000, > +0xcff7ff00, > +0xe003ff87, > +0x00470000, > +0x50800000, > +0x4007ff03, > +0xe043ff89, > +0xfc0007e0, > +0x001f8000, > +0x0007ff02, > +0xe043ff89, > +0x2ff70201, > +0xc03a0014, > +0x4007ff03, > +0xe043ff88, > +0xfc0007e0, > +0x001f8000, > +0x0007ff02, > +0xe043ff88, > +0x2ff70200, > +0xc03a0004, > +0x34070000, > +0xf0f00000, > +0xfc0007e0, > +0x001f8000, > +0x00170003, > +0x5c681000, > +0x00370002, > +0x5c980780, > +0x00370001, > +0x5c980780, > +0xfc0007e0, > +0x001f8000, > +0x00370000, > +0x5c980780, > +0x0007000f, > +0xe3000000, > diff --git a/src/shader/exacanv110.fp b/src/shader/exacanv110.fp > new file mode 100644 > index 0000000..a70d5c5 > --- /dev/null > +++ b/src/shader/exacanv110.fp > @@ -0,0 +1,47 @@ > +#ifndef ENVYAS > +static uint32_t > +NV110FP_CAComposite[] = { > + 0x00001462, /* 0x0000c000 = USES_KIL, MULTI_COLORS */ > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x80000000, /* FRAG_COORD_UMASK = 0x8 */ > + 0x00000a0a, /* FP_INTERP[0x080], 0022 0022 */ > + 0x00000000, /* FP_INTERP[0x0c0], 0 = OFF */ > + 0x00000000, /* FP_INTERP[0x100], 1 = FLAT */ > + 0x00000000, /* FP_INTERP[0x140], 2 = PERSPECTIVE */ > + 0x00000000, /* FP_INTERP[0x180], 3 = LINEAR */ > + 0x00000000, /* FP_INTERP[0x1c0] */ > + 0x00000000, /* FP_INTERP[0x200] */ > + 0x00000000, /* FP_INTERP[0x240] */ > + 0x00000000, /* FP_INTERP[0x280] */ > + 0x00000000, /* FP_INTERP[0x2c0] */ > + 0x00000000, /* FP_INTERP[0x300] */ > + 0x00000000, > + 0x0000000f, /* FP_RESULT_MASK (0x8000 Face ?) */ > + 0x00000000, /* 0x2 = FragDepth, 0x1 = SampleMask */ > +#include "exacanv110.fpc" > +}; > +#else > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > +mufu rcp $r0 $r0 > +ipa $r3 a[0x94] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r2 a[0x90] $r0 0x0 0x1 > +tex nodep $r4 $r2 0x0 0x1 t2d 0xf > +ipa $r1 a[0x84] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r0 a[0x80] $r0 0x0 0x1 > +tex nodep $r0 $r0 0x0 0x0 t2d 0xf > +depbar le 0x5 0x0 0x0 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r3 $r3 $r7 > +fmul ftz $r2 $r2 $r6 > +fmul ftz $r1 $r1 $r5 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r0 $r0 $r4 > +exit > +#endif > diff --git a/src/shader/exacanv110.fpc b/src/shader/exacanv110.fpc > new file mode 100644 > index 0000000..7c0ca5e > --- /dev/null > +++ b/src/shader/exacanv110.fpc > @@ -0,0 +1,38 @@ > +0xfc0007e0, > +0x001f8000, > +0xcff7ff00, > +0xe003ff87, > +0x00470000, > +0x50800000, > +0x4007ff03, > +0xe043ff89, > +0xfc0007e0, > +0x001f8000, > +0x0007ff02, > +0xe043ff89, > +0xaff70204, > +0xc03a0017, > +0x4007ff01, > +0xe043ff88, > +0xfc0007e0, > +0x001f8000, > +0x0007ff00, > +0xe043ff88, > +0xaff70000, > +0xc03a0007, > +0x34070000, > +0xf0f00000, > +0xfc0007e0, > +0x001f8000, > +0x00770303, > +0x5c681000, > +0x00670202, > +0x5c681000, > +0x00570101, > +0x5c681000, > +0xfc0007e0, > +0x001f8000, > +0x00470000, > +0x5c681000, > +0x0007000f, > +0xe3000000, > diff --git a/src/shader/exacmnv110.fp b/src/shader/exacmnv110.fp > new file mode 100644 > index 0000000..fe5c294 > --- /dev/null > +++ b/src/shader/exacmnv110.fp > @@ -0,0 +1,47 @@ > +#ifndef ENVYAS > +static uint32_t > +NV110FP_Composite[] = { > + 0x00001462, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x80000000, > + 0x00000a0a, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x0000000f, > + 0x00000000, > +#include "exacmnv110.fpc" > +}; > +#else > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > +mufu rcp $r0 $r0 > +ipa $r3 a[0x94] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r2 a[0x90] $r0 0x0 0x1 > +tex nodep $r4 $r2 0x0 0x1 t2d 0x8 > +ipa $r1 a[0x84] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r0 a[0x80] $r0 0x0 0x1 > +tex nodep $r0 $r0 0x0 0x0 t2d 0xf > +depbar le 0x5 0x0 0x0 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r3 $r3 $r4 > +fmul ftz $r2 $r2 $r4 > +fmul ftz $r1 $r1 $r4 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r0 $r0 $r4 > +exit > +#endif > diff --git a/src/shader/exacmnv110.fpc b/src/shader/exacmnv110.fpc > new file mode 100644 > index 0000000..9d62c1a > --- /dev/null > +++ b/src/shader/exacmnv110.fpc > @@ -0,0 +1,38 @@ > +0xfc0007e0, > +0x001f8000, > +0xcff7ff00, > +0xe003ff87, > +0x00470000, > +0x50800000, > +0x4007ff03, > +0xe043ff89, > +0xfc0007e0, > +0x001f8000, > +0x0007ff02, > +0xe043ff89, > +0x2ff70204, > +0xc03a0014, > +0x4007ff01, > +0xe043ff88, > +0xfc0007e0, > +0x001f8000, > +0x0007ff00, > +0xe043ff88, > +0xaff70000, > +0xc03a0007, > +0x34070000, > +0xf0f00000, > +0xfc0007e0, > +0x001f8000, > +0x00470303, > +0x5c681000, > +0x00470202, > +0x5c681000, > +0x00470101, > +0x5c681000, > +0xfc0007e0, > +0x001f8000, > +0x00470000, > +0x5c681000, > +0x0007000f, > +0xe3000000, > diff --git a/src/shader/exas8nv110.fp b/src/shader/exas8nv110.fp > new file mode 100644 > index 0000000..4fe2e19 > --- /dev/null > +++ b/src/shader/exas8nv110.fp > @@ -0,0 +1,42 @@ > +#ifndef ENVYAS > +static uint32_t > +NV110FP_Source_A8[] = { > + 0x00001462, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x80000000, > + 0x0000000a, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x0000000f, > + 0x00000000, > +#include "exas8nv110.fpc" > +}; > +#else > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > +mufu rcp $r0 $r0 > +ipa $r1 a[0x84] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r0 a[0x80] $r0 0x0 0x1 > +tex nodep $r0 $r0 0x0 0x0 t2d 0x8 > +depbar le 0x5 0x0 0x0 > +sched (st 0x0) (st 0x0) (st 0x0) > +mov $r3 $r0 0xf > +mov $r2 $r0 0xf > +mov $r1 $r0 0xf > +sched (st 0x0) (st 0x0) (st 0x0) > +exit > +#endif > diff --git a/src/shader/exas8nv110.fpc b/src/shader/exas8nv110.fpc > new file mode 100644 > index 0000000..1181c41 > --- /dev/null > +++ b/src/shader/exas8nv110.fpc > @@ -0,0 +1,28 @@ > +0xfc0007e0, > +0x001f8000, > +0xcff7ff00, > +0xe003ff87, > +0x00470000, > +0x50800000, > +0x4007ff01, > +0xe043ff88, > +0xfc0007e0, > +0x001f8000, > +0x0007ff00, > +0xe043ff88, > +0x2ff70000, > +0xc03a0004, > +0x34070000, > +0xf0f00000, > +0xfc0007e0, > +0x001f8000, > +0x00070003, > +0x5c980780, > +0x00070002, > +0x5c980780, > +0x00070001, > +0x5c980780, > +0xfc0007e0, > +0x001f8000, > +0x0007000f, > +0xe3000000, > diff --git a/src/shader/exasanv110.fp b/src/shader/exasanv110.fp > new file mode 100644 > index 0000000..61374a6 > --- /dev/null > +++ b/src/shader/exasanv110.fp > @@ -0,0 +1,47 @@ > +#ifndef ENVYAS > +static uint32_t > +NV110FP_CACompositeSrcAlpha[] = { > + 0x00001462, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x80000000, > + 0x00000a0a, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x0000000f, > + 0x00000000, > +#include "exasanv110.fpc" > +}; > +#else > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > +mufu rcp $r0 $r0 > +ipa $r3 a[0x84] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r2 a[0x80] $r0 0x0 0x1 > +tex nodep $r4 $r2 0x0 0x0 t2d 0x8 > +ipa $r1 a[0x94] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r0 a[0x90] $r0 0x0 0x1 > +tex nodep $r0 $r0 0x0 0x1 t2d 0xf > +depbar le 0x5 0x0 0x0 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r3 $r3 $r4 > +fmul ftz $r2 $r2 $r4 > +fmul ftz $r1 $r1 $r4 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r0 $r0 $r4 > +exit > +#endif > diff --git a/src/shader/exasanv110.fpc b/src/shader/exasanv110.fpc > new file mode 100644 > index 0000000..5516a03 > --- /dev/null > +++ b/src/shader/exasanv110.fpc > @@ -0,0 +1,38 @@ > +0xfc0007e0, > +0x001f8000, > +0xcff7ff00, > +0xe003ff87, > +0x00470000, > +0x50800000, > +0x4007ff03, > +0xe043ff88, > +0xfc0007e0, > +0x001f8000, > +0x0007ff02, > +0xe043ff88, > +0x2ff70204, > +0xc03a0004, > +0x4007ff01, > +0xe043ff89, > +0xfc0007e0, > +0x001f8000, > +0x0007ff00, > +0xe043ff89, > +0xaff70000, > +0xc03a0017, > +0x34070000, > +0xf0f00000, > +0xfc0007e0, > +0x001f8000, > +0x00470303, > +0x5c681000, > +0x00470202, > +0x5c681000, > +0x00470101, > +0x5c681000, > +0xfc0007e0, > +0x001f8000, > +0x00470000, > +0x5c681000, > +0x0007000f, > +0xe3000000, > diff --git a/src/shader/exascnv110.fp b/src/shader/exascnv110.fp > new file mode 100644 > index 0000000..90bbb55 > --- /dev/null > +++ b/src/shader/exascnv110.fp > @@ -0,0 +1,38 @@ > +#ifndef ENVYAS > +static uint32_t > +NV110FP_Source[] = { > + 0x00001462, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x80000000, > + 0x0000000a, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x0000000f, > + 0x00000000, > +#include "exascnv110.fpc" > +}; > +#else > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > +mufu rcp $r0 $r0 > +ipa $r1 a[0x84] $r0 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r0 a[0x80] $r0 0x0 0x1 > +tex nodep $r0 $r0 0x0 0x0 t2d 0xf > +depbar le 0x5 0x0 0x0 > +sched (st 0x0) (st 0x0) (st 0x0) > +exit > +#endif > diff --git a/src/shader/exascnv110.fpc b/src/shader/exascnv110.fpc > new file mode 100644 > index 0000000..2dba15d > --- /dev/null > +++ b/src/shader/exascnv110.fpc > @@ -0,0 +1,20 @@ > +0xfc0007e0, > +0x001f8000, > +0xcff7ff00, > +0xe003ff87, > +0x00470000, > +0x50800000, > +0x4007ff01, > +0xe043ff88, > +0xfc0007e0, > +0x001f8000, > +0x0007ff00, > +0xe043ff88, > +0xaff70000, > +0xc03a0007, > +0x34070000, > +0xf0f00000, > +0xfc0007e0, > +0x001f8000, > +0x0007000f, > +0xe3000000, > diff --git a/src/shader/videonv110.fp b/src/shader/videonv110.fp > new file mode 100644 > index 0000000..2728311 > --- /dev/null > +++ b/src/shader/videonv110.fp > @@ -0,0 +1,54 @@ > +#ifndef ENVYAS > +static uint32_t > +NV110FP_NV12[] = { > + 0x00001462, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x80000000, > + 0x0000000a, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x0000000f, > + 0x00000000, > +#include "videonv110.fpc" > +}; > +#else > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa pass $r2 a[0x7c] 0x0 0x0 0x1 > +mufu rcp $r2 $r2 > +ipa $r0 a[0x80] $r2 0x0 0x1 > +sched (st 0x0) (st 0x0) (st 0x0) > +ipa $r1 a[0x84] $r2 0x0 0x1 > +tex nodep $r4 $r0 0x0 0x0 t2d 0x8 > +tex nodep $r0 $r0 0x0 0x1 t2d 0xc > +sched (st 0x0) (st 0x0) (st 0x0) > +depbar le 0x5 0x1 0x1 > +fmul ftz $r5 $r4 c0[0x0] > +fadd ftz $r3 $r5 c0[0x4] > +sched (st 0x0) (st 0x0) (st 0x0) > +fadd ftz $r4 $r5 c0[0x8] > +fadd ftz $r5 $r5 c0[0xc] > +depbar le 0x5 0x0 0x0 > +sched (st 0x0) (st 0x0) (st 0x0) > +ffma ftz $r3 $r0 c0[0x10] $r3 > +ffma ftz $r4 $r0 c0[0x14] $r4 > +ffma ftz $r5 $r0 c0[0x18] $r5 > +sched (st 0x0) (st 0x0) (st 0x0) > +ffma ftz $r0 $r1 c0[0x1c] $r3 > +ffma ftz $r2 $r1 c0[0x24] $r5 > +ffma ftz $r1 $r1 c0[0x20] $r4 > +sched (st 0x0) (st 0x0) (st 0x0) > +exit > +#endif > diff --git a/src/shader/videonv110.fpc b/src/shader/videonv110.fpc > new file mode 100644 > index 0000000..31d745a > --- /dev/null > +++ b/src/shader/videonv110.fpc > @@ -0,0 +1,52 @@ > +0xfc0007e0, > +0x001f8000, > +0xcff7ff02, > +0xe003ff87, > +0x00470202, > +0x50800000, > +0x0027ff00, > +0xe043ff88, > +0xfc0007e0, > +0x001f8000, > +0x4027ff01, > +0xe043ff88, > +0x2ff70004, > +0xc03a0004, > +0x2ff70000, > +0xc03a0016, > +0xfc0007e0, > +0x001f8000, > +0x34170001, > +0xf0f00000, > +0x00070405, > +0x4c681000, > +0x00170503, > +0x4c581000, > +0xfc0007e0, > +0x001f8000, > +0x00270504, > +0x4c581000, > +0x00370505, > +0x4c581000, > +0x34070000, > +0xf0f00000, > +0xfc0007e0, > +0x001f8000, > +0x00470003, > +0x49a00180, > +0x00570004, > +0x49a00200, > +0x00670005, > +0x49a00280, > +0xfc0007e0, > +0x001f8000, > +0x00770100, > +0x49a00180, > +0x00970102, > +0x49a00280, > +0x00870101, > +0x49a00200, > +0xfc0007e0, > +0x001f8000, > +0x0007000f, > +0xe3000000, > diff --git a/src/shader/xfrm2nv110.vp b/src/shader/xfrm2nv110.vp > new file mode 100644 > index 0000000..bbfc527 > --- /dev/null > +++ b/src/shader/xfrm2nv110.vp > @@ -0,0 +1,82 @@ > +#ifndef ENVYAS > +static uint32_t > +NV110VP_Transform2[] = { > + 0x02000461, > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x000ff000, > + 0x00000000, /* VP_ATTR_EN[0x000] */ > + 0x00000000, /* VP_ATTR_EN[0x080] */ > + 0x00000000, /* VP_ATTR_EN[0x100] */ > + 0x00000000, > + 0x00000000, /* VP_ATTR_EN[0x200] */ > + 0x80000000, /* VERTEXID */ > + 0x00000000, /* VP_ATTR_EN[0x300] */ > + 0x00000000, > + 0x0033f000, /* VP_EXPORT_EN[0x040] */ > + 0x00000000, /* VP_EXPORT_EN[0x0c0] */ > + 0x00000000, > + 0x00000000, > + 0x00000000, > + 0x00000000, /* VP_EXPORT_EN[0x2c0] */ > + 0x00000000, > +#include "xfrm2nv110.vpc" > +}; > +#else > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ld b32 $r5 a[0x2fc] 0x0 > +shl $r5 $r5 0x5 > +ld b64 $r0 c0[$r5+0x80] > +sched (st 0x0) (st 0x0) (st 0x0) > +ld b64 $r2 c0[$r5+0x88] > +st b128 a[0x70] $r0 0x0 > + > +ld b64 $r0 c0[$r5+0x90] > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r2 $r0 c0[0x0] > +fmul ftz $r3 $r0 c0[0xc] > +fmul ftz $r4 $r0 c0[0x18] > +sched (st 0x0) (st 0x0) (st 0x0) > +ffma ftz $r2 $r1 c0[0x4] $r2 > +ffma ftz $r3 $r1 c0[0x10] $r3 > +ffma ftz $r4 $r1 c0[0x1c] $r4 > +sched (st 0x0) (st 0x0) (st 0x0) > +fadd ftz $r2 $r2 c0[0x8] > +fadd ftz $r3 $r3 c0[0x14] > +fadd ftz $r4 $r4 c0[0x20] > +sched (st 0x0) (st 0x0) (st 0x0) > +mufu rcp $r4 $r4 > +fmul ftz $r2 $r2 $r4 > +fmul ftz $r3 $r3 $r4 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r0 $r2 c0[0x24] > +fmul ftz $r1 $r3 c0[0x28] > +st b64 a[0x80] $r0 0x0 > + > +sched (st 0x0) (st 0x0) (st 0x0) > +ld b64 $r0 c0[$r5+0x98] > +fmul ftz $r2 $r0 c0[0x2c] > +fmul ftz $r3 $r0 c0[0x38] > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r4 $r0 c0[0x44] > +ffma ftz $r2 $r1 c0[0x30] $r2 > +ffma ftz $r3 $r1 c0[0x3c] $r3 > +sched (st 0x0) (st 0x0) (st 0x0) > +ffma ftz $r4 $r1 c0[0x48] $r4 > +fadd ftz $r2 $r2 c0[0x34] > +fadd ftz $r3 $r3 c0[0x40] > +sched (st 0x0) (st 0x0) (st 0x0) > +fadd ftz $r4 $r4 c0[0x4c] > +mufu rcp $r4 $r4 > +fmul ftz $r2 $r2 $r4 > +sched (st 0x0) (st 0x0) (st 0x0) > +fmul ftz $r3 $r3 $r4 > +fmul ftz $r0 $r2 c0[0x50] > +fmul ftz $r1 $r3 c0[0x54] > +sched (st 0x0) (st 0x0) (st 0x0) > +st b64 a[0x90] $r0 0x0 > + > +exit > +#endif > diff --git a/src/shader/xfrm2nv110.vpc b/src/shader/xfrm2nv110.vpc > new file mode 100644 > index 0000000..0d9ebfd > --- /dev/null > +++ b/src/shader/xfrm2nv110.vpc > @@ -0,0 +1,102 @@ > +0xfc0007e0, > +0x001f8000, > +0x2fc7ff05, > +0xefd87f80, > +0x00570505, > +0x38480000, > +0x08070500, > +0xef950000, > +0xfc0007e0, > +0x001f8000, > +0x08870502, > +0xef950000, > +0x0707ff00, > +0xeff1ff80, > +0x09070500, > +0xef950000, > +0xfc0007e0, > +0x001f8000, > +0x00070002, > +0x4c681000, > +0x00370003, > +0x4c681000, > +0x00670004, > +0x4c681000, > +0xfc0007e0, > +0x001f8000, > +0x00170102, > +0x49a00100, > +0x00470103, > +0x49a00180, > +0x00770104, > +0x49a00200, > +0xfc0007e0, > +0x001f8000, > +0x00270202, > +0x4c581000, > +0x00570303, > +0x4c581000, > +0x00870404, > +0x4c581000, > +0xfc0007e0, > +0x001f8000, > +0x00470404, > +0x50800000, > +0x00470202, > +0x5c681000, > +0x00470303, > +0x5c681000, > +0xfc0007e0, > +0x001f8000, > +0x00970200, > +0x4c681000, > +0x00a70301, > +0x4c681000, > +0x0807ff00, > +0xeff0ff80, > +0xfc0007e0, > +0x001f8000, > +0x09870500, > +0xef950000, > +0x00b70002, > +0x4c681000, > +0x00e70003, > +0x4c681000, > +0xfc0007e0, > +0x001f8000, > +0x01170004, > +0x4c681000, > +0x00c70102, > +0x49a00100, > +0x00f70103, > +0x49a00180, > +0xfc0007e0, > +0x001f8000, > +0x01270104, > +0x49a00200, > +0x00d70202, > +0x4c581000, > +0x01070303, > +0x4c581000, > +0xfc0007e0, > +0x001f8000, > +0x01370404, > +0x4c581000, > +0x00470404, > +0x50800000, > +0x00470202, > +0x5c681000, > +0xfc0007e0, > +0x001f8000, > +0x00470303, > +0x5c681000, > +0x01470200, > +0x4c681000, > +0x01570301, > +0x4c681000, > +0xfc0007e0, > +0x001f8000, > +0x0907ff00, > +0xeff0ff80, > +0x0007000f, > +0xe3000000, >
Apparently Analagous Threads
- [PATCH 5/5] recognize and accelerate GM20x
- [PATCH 5/5] recognize and accelerate GM20x
- [PATCH xf86-video-nouveau] Add Pascal family support, identical to Maxwell
- [PATCH xf86-video-nouveau v2] Add Pascal family support, identical to Maxwell
- [PATCH v2 1/7] exa: add GM10x acceleration support