search for: l3

Is it even possible or even worth while to do layer 3 switching (bridging) on a Linux system? Or would this be considered routing even though everything is done on OSI Layer 2? Which would be faster, Layer 3 switching (bridging) on OSI Layer 2 or routing on OSI Layer 3? Grant. . . .

...r.c:757 Successors according to CFG: BB#5 BB#4 is compiled down to ! BB#7: ! %bb ! in Loop: Header=BB1_2 Depth=2 sethi 1856, %l5 or %g0, 1, %l6 sll %l6, %l3, %l3 or %l5, 1, %l5 and %l3, %l5, %l3 subcc %l3, 0, %l3 bne .LBB1_8 nop ba .LBB1_68 nop ! BB#8: ! %bb1 ! in Loop: Header=BB1_2 De...

Hi, Chris > That is target independent code, so you should not put sparc specific changes there.  It sounds like one of the sparc-specific target hooks is wrong. Since sparc does not provide any hooks for operation of branches (e.g. AnalyzeBranch and friends) it might be possible that generic codegen code is broken in absence of these hooks. -- With best regards, Anton Korobeynikov Faculty

...levels vs. responses; the levels are sorted by responses but levels vary from one panel to another. However, I run into problems with controlling the y-limits and y-labels. In particular, suppose I have a data frame rsp <- c(10,2,4,0,2,3) lvl <- factor(c("L1","L2","L3","L2","L3","L4"),levels=c("L1","L2","L3","L4")) cat <- factor(c("A","A","A","B","B","B"),levels=c("A","B")) xx <- data.frame(cat,lvl,rsp)...

Shamelessly reusing the announcement Arnaud sent about three months ago for nut-2.2.1: "We're preparing to release 2.2.1-pre2, so if you have some fixes to backport on Testing, consider announcing it and doing asap. As always, compatibilities update and bugfixes only!" Regards, Arjen -- Eindhoven - The Netherlands Key fingerprint - 66 4E 03 2C 9D B5 CB 9B 7A FE 7E C1

Hi, How does the requirement that phi instructions have one value per predecessor basic block interact with indirectbr instructions? For instance, take the following code: L1: br i1 %somevalue, label %L2, label %L3 L2: %ret1 = i8* blockaddress(@myfunction, %L5) br label %L4 L3: %ret2 = i8* blockaddress(@myfunction, %L6) br label %L4 L4: %ret = phi i8* [%ret1, L2], [%ret2, L3] indirectbr i8* %ret, [label %L5, label %L6] L5: %myval = phi i32 [0, %L2], [1, %L3] ; are both of these values req...

...validate all 512 entries (in order to avoid making available translations that could be used during speculative execution), the validation has the potential to fail (and does in reality), resulting in the guest dying. The only option I presently see is to special case the compatibility guest in the l3 handling and (I really hate to do that) clear out the 518 supposedly unused entries (or at least clear their present bits), meaning that no guest may ever make clever assumptions and try to store some other data in the unused portion of the pgd page. Thanks for sharing any other ideas on how to ov...

...find a matrix, which includes the values of l1, without the rows of l2, #which has equal entities (the index of the additional NA?S). #In this example the result should be row 3 of l1 with the values 4 and 1. #The following code works, but I think there must be a much more elegant way to do this. l3 <- l1 l3 <- cbind( l1, rep(0, nrow(l1)) ) num <- 1 for( i in 1:nrow(l1) ){ for( j in 1:nrow(l2) ){ if( l1[i,1] == l2[j,1] & l1[i,2] == l2[j,2]){ l3[i,3] <- 1 } } } l4 <- l3[l3[,3]==0, c(1,2)] #> l4 #row col # 4 1 I have often such problems like t...

...label > being omitted (assuming multiple branches are legal in an MBB). It > appears that the branch delay-slots are specifically to blame here Yes, most certainly. > - the above BB#315 immediately prior to output is > > BB#7: derived from LLVM BB %bb > Live Ins: %L1 %L0 %L3 %L2 %L4 > Predecessors according to CFG: BB#6 > %L5<def> = SETHIi 1856 > %L6<def> = ORri %G0, 1 > %L3<def> = SLLrr %L6<kill>, %L3<kill> > %L5<def> = ORri %L5<kill>, 1 > %L3<def> = ANDrr %L3<ki...

...The data > for the voltages is not what I'm expecting, and I am wondering how I > should interpret it. Wow, that sounds kind of industrial. Model? Is the input an L14-20P? Or equivalent non-twistlock? > Here is an example from upsc: > > input.L1-L2.voltage: 121 > input.L2-L3.voltage: 120 > input.voltage: 121.20 > output.current: 5.90 > output.L1-L2.voltage: 119 > output.L1.current: 5.90 > output.L2-L3.voltage: 119 > output.L2.current: 1 > > The "input.voltage" value doesn't reflect the 240 volts that is > actually being applied....

...arameter.pollinterval: 2 driver.parameter.port: /dev/ttyS0 driver.version: 2.4.3-2432M driver.version.internal: 0.02 input.bypass.frequency: 50.0 input.frequency.nominal: 50.0 input.frequency: 50.0 input.L1-N.voltage: 235.9 input.L1.current: 5.0 input.L2-N.voltage: 239.6 input.L2.current: 5.4 input.L3-N.voltage: 237.8 input.L3.current: 5.0 input.phases: 3 output.frequency.nominal: 50.0 output.frequency: 50.0 output.L1-N.voltage: 230.8 output.L1.crestfactor: 2.1 output.L2-N.voltage: 230.4 output.L2.crestfactor: 2.7 output.L3-N.voltage: 230.4 output.L3.crestfactor: 2.0 output.phases: 3 ups.delay.s...

...; preds = %entrypoint br label %L2 L2: ; preds = %L0, %L1 %2 = phi i64 [ %arg0, %L1 ], [ %0, %L0 ] %3 = phi i64 [ %arg1, %L1 ], [ %1, %L0 ] %4 = sdiv i64 %2, 4 %5 = sdiv i64 %3, 4 br label %L5 L3: ; preds = %L3, %L5 %6 = phi i64 [ %15, %L3 ], [ 0, %L5 ] %7 = mul i64 %19, 4 %8 = add nsw i64 %7, %6 %9 = getelementptr float* %arg5, i64 %8 %10 = load float* %9 %11 = getelementptr float* %arg6, i64 %8 %12 = load float* %11 %13...

Greetings Please forgive the OT question yet I highly value the experience and wisdom on this list I am wondering if anyone here can address the performance difference between having a processor board with say 256KB L2 *and* 2048KB L3 cache *VERSUS* just having the same processor board with just the L2 cache in a centos server environment... Please figure that all other necessary and related componentry is well above needed amounts and high performance specs for a professional server environment. Thanks in advance!! - rh --...

...and some attributes at that location. The second table has the same locations, but only once with a different set of attributes. I would like to add the second set of attributes to the first table. Example: set.seed <- 123 loc <- c(rep("L1", 3), rep("L2", 5), rep("L3", 2)) val1 <- round(rnorm(10),2) val2 <- c("a", "b", "c", "a", "b", "d", "f", "e", "b", "e") t1 <- data.frame(loc, val1, val2) t2 <- data.frame(loc=c("L1","L2",&q...

...; preds = %entrypoint > br label %L2 > > L2: ; preds = %L0, %L1 > %2 = phi i64 [ %arg0, %L1 ], [ %0, %L0 ] > %3 = phi i64 [ %arg1, %L1 ], [ %1, %L0 ] > %4 = sdiv i64 %2, 4 > %5 = sdiv i64 %3, 4 > br label %L5 > > L3: ; preds = %L3, %L5 > %6 = phi i64 [ %15, %L3 ], [ 0, %L5 ] > %7 = mul i64 %19, 4 > %8 = add nsw i64 %7, %6 > %9 = getelementptr float* %arg5, i64 %8 > %10 = load float* %9 > %11 = getelementptr float* %arg6, i64 %8 > %12 = l...

Hi all! I'm wondering if there's anyone doing any hacking on the snmp-ups driver at the moment. I've started looking at implementing 3phase-support, and this uncovered some rather unpleasant stuff in the snmp-ups driver that I really need to fix in order to get things sane. Those of you that's allergic to SNMP might want to stop reading now, this is rather icky ;)

...ion: v2c driver.version: 2.7.2 driver.version.data: ietf MIB 1.4 driver.version.internal: 0.72 input.bypass.L1-N.voltage: 236.00 input.bypass.L1.current: 0.00 input.bypass.L1.realpower: 0.00 input.bypass.L2-N.voltage: 237.00 input.bypass.L2.current: 0.00 input.bypass.L2.realpower: 0.00 input.bypass.L3-N.voltage: 236.00 input.bypass.L3.current: 0.00 input.bypass.L3.realpower: 0.00 input.bypass.phases: 3.00 input.frequency.nominal: 0.00 input.L1-N.voltage: 236.00 input.L1.current: 11.00 input.L1.frequency: 50.00 input.L1.realpower: 0.00 input.L2-N.voltage: 237.00 input.L2.current: 10.50 input.L2.f...

...s rewritten as two loops. This avoids the 'rem' and 'div' instructions in the index calculation (which give the loop vectorizer a hard time). However, with this setup the loop vectorizer complains about a too small loop. LV: Checking a loop in "main" LV: Found a loop: L3 LV: Found a loop with a very small trip count. This loop is not worth vectorizing. LV: Not vectorizing. Here the IR: define void @main(i64 %arg0, i64 %arg1, i1 %arg2, i64 %arg3, float* noalias %arg4, float* noalias %arg5, float* noalias %arg6) { entrypoint: br i1 %arg2, label %L0, label %L2...

...ndef" with speculative loads in a concurrent setting with separate >> undefs? > > The intention is that they should have the same semantics. Suppose there are three threads T1, T2 and T3, T1 (S1 )stores to a location l as non-atomic, T2 then (S2)stores to l as SC-atomic, later T3 (L3)loads from l as SC-atomic. I think the load @ T3 should return undef, since it can see both writes from T1 T2. Then the question is if the SC store @ T2 --- S2 and the SC load @ T3 --- L3 introduces an acq/rel (synchronized-with) edge. This will affect if later conflicting accesses are ordered or...

...one that provides two legs of 120v output from two legs of 120 input, and what is seen as "L2" is actually neutral, and the line names are reporting incorrectly. With that in mind, each leg in should be 120v, as well as the outputs, which is exactly what you are seeing.(The fact tht L1 to L3 is 240v really isn't relevant). - Tim On November 11, 2024 6:56:51 PM EST, Greg Troxel via Nut-upsuser <nut-upsuser at alioth-lists.debian.net> wrote: >John Ackermann N8UR via Nut-upsuser ><nut-upsuser at alioth-lists.debian.net> writes: > >> I am monitoring via the...