search for: encodermethod

...2010 at 8:03 AM, Jim Grosbach <grosbach at apple.com> wrote: > Sorta. getBinaryCodeForInst() is auto-generated by tablegen, so shouldn't be modified directly. The target can register hooks for instruction operands for any special encoding needs, including registering fixups, using the EncoderMethod string. For an example, have a look at the LDRi12 instruction and how it registers a fixup for the addrmode_imm12 operand when it needs one. Hi Jim,. follow up question for ya: The current movt/movw pair (as defined in ARMInstrInfo.td) does not use EncoderMethod string to declare a special case...

...rmediate node type for a shifted >> address? >> > > Technically yes, but the list of allowed types is limited. "RegisterClass" > (e.g GPRC) is allowed, as is "Operand" (e.g. i64imm). > > You can create a subclass of "Operand" and provide your EncoderMethod for > it. > > > Followup question: I was thinking that in order to match this DAG: 0x30d29c0: i64 = Constant<3> 0x30d2e00: i64 = shl 0x30d2be0, 0x30d29c0 [ORD=3] 0x30d2f10: i64 = add 0x30d2cf0, 0x30d2e00 [ORD=3] 0x30d28b0: <multiple use>...

...er. On the other hand, if MC objects are to model the encoding, one would expect the MCOperand for the 16-bit encoding to contain a number between -1024 and 1023. Which one is it? My intuition says the MCOperand should model the assembly syntax and contain the 32-bit signed integer, and that the EncoderMethod and DecoderMethod are responsible for mapping that high-level number to the low-level binary representation. If, however, the MCOperand models the encoding, then EncoderMethod and DecoderMethod glue need not exist, and that bit-twiddling logic would be pushed to whoever creates the MCOperand. Loo...

I'm attempting to implement codegen support for the AVR ST/LD <http://www.atmel.com/webdoc/avrassembler/avrassembler.wb_ST.html> family of instructions. The binary encoding is not particularly consistent -- take a look at this table of variants of LD, along with their machine code representation: # load 8 bits from pointer register X into general purpose Rd ld Rd, X `1001 000d dddd

I can't get it to work with pattern matching. My operand is defined like so: def LDSTPtrReg : Operand<i16> { let MIOperandInfo = (ops PTRREGS); let EncoderMethod = "encodeLDSTPtrReg"; } I am able to use it in the place of PTRREGS in the definition of the LD instruction, but if I use it in an instruction matching pattern, compilation fails with the error "Unknown leaf kind: LDSTPtrReg:i16:$ptrreg". On Sun, Feb 1, 2015 at 10:26 AM, Dyla...

But don't the defs for ADDR_RR and ADDR_RI also contain dags? def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; Do I need to create some other intermediate node type for a shifted address? Phil On

...and I have def pcoffset8 : Operand<i8>, ImmLeaf<i8, [{ return Immediate >= -128 && Immediate <= 127; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i8imm); let ParserMatchClass = ImmediateAsmOperand<"Imm8">; let EncoderMethod = "getMemOpValue"; let DecoderMethod = "DecodeMemOperand"; } def pcoffset16 : Operand<i16>, ImmLeaf<i16, [{ return Immediate >= -32768 && Immediate <= 32767; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i16im...

...etween the PICBase (.L1$pb) and the GOT. This works fine when generating assembly output, but it fails when generating ELF output, with the error "Cannot represent a difference across sections" (line 847, lib/MC/ELFObjectWriter.cpp). Roman Divacky suggested I try something with 'let EncoderMethod = ...' similar to how the TOC entries are done for ppc64. However, I'm not sure if that would work, given that the TOC on ppc64 is handled differently from the GOT on ppc32, and I'm not sure how to represent that if it could work. Any ideas on how a cross-section diff and relocation c...

...objects > are to model the encoding, one would expect the MCOperand for the > 16-bit encoding to contain a number between -1024 and 1023. Which one > is it? > > My intuition says the MCOperand should model the assembly syntax and > contain the 32-bit signed integer, and that the EncoderMethod and > DecoderMethod are responsible for mapping that high-level number to > the low-level binary representation. If, however, the MCOperand > models the encoding, then EncoderMethod and DecoderMethod glue need > not exist, and that bit-twiddling logic would be pushed to whoever > cr...

...am confused as to how "ptroff" and "ptrreg" get matched with "memri" used in STWU? For reference[1] memri is defined as: def memri :Operand<iPTR> { let PrintMethod = "printMemRegImm"; let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); let EncoderMethod = "getMemRIEncoding";} [1] https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?view=markup -- * Anitha* -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130407/e6eb65...

...td as BNONE32(ins jmptarget:$addr), Branch32 class - Branch32 class is defined in EpiphanyInstrFormats.td with bits<24> addr, which should go into bits{31-8} of the MC instruction. Those bits remain zeros after relaxation for some reason. - jmptarget operand has type OPERAND_PCREL, and uses EncoderMethod "getJumpTargetOpValue" defined in EpiphanyMCCodeEmitter. If this method gets MCExpr, it creates fixup, and I can see this fixup in debug. - Fixup is called fixup_Epiphany_PCREL24, and is defined in EpiphanyFixupKinds and EpiphanyAsmBackend, with FKF_IsPCRel flag. Can someone please te...

...t;ptrreg" get matched with "memri" used in STWU? > > > For reference[1] memri is defined as: > > def memri :Operand<iPTR> { > > let PrintMethod = "printMemRegImm"; > > let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); > > let EncoderMethod = "getMemRIEncoding"; > > } > > [1] > https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?view=markup > -- > /* Anitha*/ > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at c...

...D_DESC : LD_DESC_BASE<"ldvd", load, v32i16, MSA128DOpnd>; I've tried to change mem_msa to hold only let MIOperandInfo = (ops simm10) but there are problems it seems: // MSA specific address operand def mem_msa : mem_generic { let MIOperandInfo = (ops ptr_rc, simm10); let EncoderMethod = "getMSAMemEncoding"; } Could you please tell me what is the simplest way to define in LD_DESC_BASE a $addrsrc that is just an immediate value like i16 or i16imm? Thank you very much, Alex

...trreg" > get matched with "memri" used in STWU? > > > For reference[1] memri is defined as: > > def memri :Operand<iPTR> { > > let PrintMethod = "printMemRegImm"; > > let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); > > let EncoderMethod = "getMemRIEncoding"; > } > > [1] > https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?view=markup > -- > Anitha > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu...

...      gslbx           $2,0($3,$4)                                       ^ I just copy-n-paste  mem_generic  and  getMemEncoding: def gs_mem : Operand<iPTR> {   let PrintMethod = "printMemOperand";   let MIOperandInfo = (ops ptr_rc, ptr_rc, simm16); ^-- for two registers   let EncoderMethod = "getGSMemEncoding";                                             ^-- just encoding two registers and one offset   let ParserMatchClass = MipsMemAsmOperand;   let OperandType = "OPERAND_MEMORY"; } ----- 8< -------- 8< -------- 8< -------- 8< -------- 8< ----...

...;t find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPRegs, GPRegs); let EncoderMethod = "getMemEncoding"; } def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; def LDRAM : FG1<0b000001, (outs GPRegs:$dst), (ins mem:$src), "ldram $dst,$src", [(set GPRegs:$dst, (load addr:$src))]>; def STRAM : FG1<0b000010, (ou...

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand";

...thing like I had in ADDR_SHLI definition: >> def ADDR_SHLI : Addr< 2, "SelectAddrShlImm", >> (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >; >> >> >> Now If I have to create a subclass of Operand and define it's >> EncoderMethod in C++, does that mean the pattern matching (matching the >> shift left and add) now happens on the C++ side as well? >> > > Actually the EncoderMethod is probably not needed for this case. I thought > you had a scaled immediate that needs to be shifted during encoding. > &g...

...GOT. This works fine when generating assembly output, but it fails >> when generating ELF output, with the error "Cannot represent a >> difference across sections" (line 847, lib/MC/ELFObjectWriter.cpp). >> >> Roman Divacky suggested I try something with 'let EncoderMethod = ...' >> similar to how the TOC entries are done for ppc64. However, I'm not >> sure if that would work, given that the TOC on ppc64 is handled >> differently from the GOT on ppc32, and I'm not sure how to represent >> that if it could work. >> >> A...

...$R), bb:$T)>;* *def BGEID : TBT<0b101110, (outs), (ins GR32:$ra, brtarget:$offset), "bgeid\t$ra,$offset", [], IIC_BRc> {* * let rd = 0b10101;* *}* *def brtarget : Operand<OtherVT>* *{* * let PrintMethod = "printPCRelImmOperand";* * let EncoderMethod = "getBranchTargetOpValue";* * let OperandType = "OPERAND_PCREL";* * let DecoderMethod = "DecodeBranchTarget";* *}* *getBranchTargetOpValue**(const MCInst &MI, unsigned OpNo,* * SmallVectorImpl<MCFixup> &Fixups,* *...