search for: decodermethod

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))&gt...

...hand, if MC objects are to model the encoding, one would expect the MCOperand for the 16-bit encoding to contain a number between -1024 and 1023. Which one is it? My intuition says the MCOperand should model the assembly syntax and contain the 32-bit signed integer, and that the EncoderMethod and DecoderMethod are responsible for mapping that high-level number to the low-level binary representation. If, however, the MCOperand models the encoding, then EncoderMethod and DecoderMethod glue need not exist, and that bit-twiddling logic would be pushed to whoever creates the MCOperand. Looking at the Thumb...

.....2] × 3 + op3[3..2] bb = op1[1..0] cc = op2[1..0] dd = op3[1..0] op1 - op3 are all in the range 0-11 and therefore aaaaa is in the range 0 - 26 I managed to get decoding of ADD_3r instructions to work by specifying the value of the bits that are fixed in the instruction format and using a custom DecoderMethod to handle the rest. The problem comes when I try and add the INITSP_2r instruction. INITSP_2r is encoded as: 00010aaaaab0ccdd Again operands are not individually encoded into bits but instead they are combined into a single field using arithmetic operations. Due to the way the aaaaa is derived it...

...mmLeaf<i8, [{ return Immediate >= -128 && Immediate <= 127; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i8imm); let ParserMatchClass = ImmediateAsmOperand<"Imm8">; let EncoderMethod = "getMemOpValue"; let DecoderMethod = "DecodeMemOperand"; } def pcoffset16 : Operand<i16>, ImmLeaf<i16, [{ return Immediate >= -32768 && Immediate <= 32767; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i16imm); let ParserMatchClass = ImmediateAsmOperand&...

...1..0] > cc = op2[1..0] > dd = op3[1..0] > > op1 - op3 are all in the range 0-11 and therefore aaaaa is in the range 0 - 26 > > I managed to get decoding of ADD_3r instructions to work by specifying the value of the bits that are fixed in the instruction format and using a custom DecoderMethod to handle the rest. The problem comes when I try and add the INITSP_2r instruction. > > INITSP_2r is encoded as: 00010aaaaab0ccdd > > Again operands are not individually encoded into bits but instead they are combined into a single field using arithmetic operations. Due to the way the...

...el the encoding, one would expect the MCOperand for the > 16-bit encoding to contain a number between -1024 and 1023. Which one > is it? > > My intuition says the MCOperand should model the assembly syntax and > contain the 32-bit signed integer, and that the EncoderMethod and > DecoderMethod are responsible for mapping that high-level number to > the low-level binary representation. If, however, the MCOperand > models the encoding, then EncoderMethod and DecoderMethod glue need > not exist, and that bit-twiddling logic would be pushed to whoever > creates the MCOperand. &g...

...NoItinerary> { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addrsrc); string AsmString = !strconcat("mov $wd, ($addrsrc)"); list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))]; InstrItinClass Itinerary = itin; string DecoderMethod = "DecodeMSA128Mem"; } class LD_D_DESC : LD_DESC_BASE<"ldvd", load, v32i16, MSA128DOpnd>; I've tried to change mem_msa to hold only let MIOperandInfo = (ops simm10) but there are problems it seems: // MSA specific address operand def mem_msa : mem_generic { le...

...icts with a non-VLE instruction and I receive an error during generation of disassembler tables. My question is how to resolve this decoding conflict? One option I considered would be to remove all non-VLE instructions but I would like to avoid that. Another option would perhaps be to set a custom DecoderMethod but if possible I would rather do this in TableGen. Any pointers for how to proceed with this is appreciated. - David

...16u). We are using uimm16 not match unsigned but for PrintMethod, effectively uimm16 and simm16 are both Operand<i16>. I'm still unclear why simm16 matches and uimm16 does not. Here is the pattern if that helps at all. So just as a reference: def simm16 : Operand<i16> { let DecoderMethod= "DecodeSimm16"; let OperandType = "OPERAND_IMMEDIATE"; } def uimm16 : Operand<i16> { let PrintMethod = "printUnsignedImm"; let OperandType = "OPERAND_IMMEDIATE"; } def immSExt16x : ImmLeaf<i16, [{ return isInt<16>(Imm); }]>; de...

...nOperandList = (ins ROWD:$wd, MemOpnd:$addrdst); string AsmString = !strconcat("LS[$addrdst] = $wd;", instr_asm); list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addrdst)]; InstrItinClass Itinerary = itin; string DecoderMethod = "DecodeMSA128Mem"; } Also, BPF has its own scalar stores and loads (with the standard i64 registers), for example (from https://github.com/llvm-mirror/llvm/blob/master/lib/Target/BPF/BPFInstrInfo.td): class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag O...

Hello James, that was also what I've planned to do but just wasn't sure. Thanks for that. On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk> wrote: > Hi, > > You can't nest operands like that - it must be a flattened list. So: > > def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm), > (ops (i32 14), (i32

Hi, I've instruction scheduling problem that I cannot further investigate by myself... Could someone give me some clues? After Instruction selection, here is part of the generated instruction. NOP MOV_AB_ro @s1, %fab_roff0 %6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6 MOV_A_oo %6, def %5; FPUaOffsetClass:%6,%5 MOVSUTO_A_iSLo 24575, def %7;

...nOperandList = (ins ROWD:$wd, MemOpnd:$addrdst); string AsmString = !strconcat("LS[$addrdst] = $wd;", instr_asm); list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addrdst)]; InstrItinClass Itinerary = itin; string DecoderMethod = "DecodeMSA128Mem"; } Also, BPF has its own scalar stores and loads (with the standard i64 registers), for example (from https://github.com/llvm-mirror/llvm/blob/master/lib/Target/BPF/BPFInstrInfo.td): class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag Op...

...6 and simm16 are both Operand<i16>. I'm still unclear >> why >> simm16 matches and uimm16 does not. Here is the pattern if that helps >> at >> all. >> >> So just as a reference: >> >> def simm16 : Operand<i16> { >> let DecoderMethod= "DecodeSimm16"; >> let OperandType = "OPERAND_IMMEDIATE"; >> } >> >> def uimm16 : Operand<i16> { >> let PrintMethod = "printUnsignedImm"; >> let OperandType = "OPERAND_IMMEDIATE"; >> } >> &gt...

...ROWSP:$wsp, VK128Opnd:$wsm, ROWSI:$wsptr, ROWSI:$wsi); string AsmString = "$wd = LS[R($wsi )];"; list<dag> Pattern = [(set ROWD:$wd, (TyNode (masked_gather ROWSP:$wsp, VK128Opnd :$wsm, ROWSI:$wsptr, ROWSI:$wsi)))]; InstrItinClass Itinerary = itin; string DecoderMethod = "DecodeMSA128Mem"; } class LD_INDIRECT_D_DESC2 : LD_INDIRECT_DESC_BASE2<"read", v128i16, MSA128DOpnd>; class LD_INDIRECT_D_ENC2 : MSA_2R_FMT<0b101001110>; def LD_INDIRECT_D2: LD_INDIRECT_D_ENC2, LD_INDIRECT_D_DESC2; /* // From http://...

Hi all, I started to write an LLVM backend for custom CPU. I created XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPRegs, GPRegs); let EncoderMethod = "getMemEncoding"; } def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], [SDNPWantPar...

...instr_asm); > list<dag> Pattern = [(set ROWD:$wd, VK128Opnd:$wdm, > (masked_gather > ROWSP:$wsp, VK128Opnd:$wsm, vectoraddr:$wsi))]; > > InstrItinClass Itinerary = itin; > string DecoderMethod = "DecodeMSA128Mem"; > } > class LD_INDIRECT_D_DESC2 : LD_INDIRECT_DESC_BASE2<"read", MSA128DOpnd>; > class LD_INDIRECT_D_ENC2 : MSA_3R_FMT<0b101001110>; > def LD_INDIRECT_D2: LD_INDIRECT_D_ENC2, LD_INDIRECT_D_DESC2; > &...

...uot;, instr_asm); list<dag> Pattern = [(set ROWD:$wd, VK128Opnd:$wdm, (masked_gather ROWSP:$wsp, VK128Opnd:$wsm, vectoraddr:$wsi))]; InstrItinClass Itinerary = itin; string DecoderMethod = "DecodeMSA128Mem"; } class LD_INDIRECT_D_DESC2 : LD_INDIRECT_DESC_BASE2<"read", MSA128DOpnd>; class LD_INDIRECT_D_ENC2 : MSA_3R_FMT<0b101001110>; def LD_INDIRECT_D2: LD_INDIRECT_D_ENC2, LD_INDIRECT_D_DESC2; Unfortunately,...

...and where a dag node expects two operands. :( def Bcc : ABI<0b1010, (outs), (ins br_target:$target), IIC_Br, "b", "\t$target", [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> { bits<24> target; let Inst{23-0} = target; let DecoderMethod = "DecodeBranchImmInstruction"; } // FIXME: should be able to write a pattern for ARMcmov, but can't use // a two-value operand where a dag node expects two operands. :( let neverHasSideEffects = 1 in { def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p...

...d\t$ra,$offset", [], IIC_BRc> {* * let rd = 0b10101;* *}* *def brtarget : Operand<OtherVT>* *{* * let PrintMethod = "printPCRelImmOperand";* * let EncoderMethod = "getBranchTargetOpValue";* * let OperandType = "OPERAND_PCREL";* * let DecoderMethod = "DecodeBranchTarget";* *}* *getBranchTargetOpValue**(const MCInst &MI, unsigned OpNo,* * SmallVectorImpl<MCFixup> &Fixups,* * const MCSubtargetInfo &STI) const {* * const MCOperand &MO = MI.getOperand(OpNo);*...