So I thought I'd try to use the documentation on llvm backends to try to
create a DLX backend. I think I've got most of the stuff for the .td files
done but I've got some problems.
* Do I need to represent the PC in my XXXRegisterInfo.td file; the branch
instruction effects it but you can directly access it ... I'm thinking not.
* In my Instruction subclasses (in XXXInstrFormats.td) how do I get the
register number/immediate values from the "ins" dag?
* Whats the SDNode value for the conditional instructions e.g. icmp eq i32 ...
except that doesn't work.
* How horrifically wrong do my implementations of SWri, LWri, LLOri, and LHri
look?
* Is my implementation of the calling convention correct? I'm after first
6 registers then using a 32bit aligned stack; with r1 for return address
heres what I've got so far ... all advice, pointers etc very very welcome.
Rich
** DLX.td *********************************************************
//===- DLX.td - Target definition file for the DLX ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This is a target description file for the DLX RISC processor architecture,
// designed by John L. Hennessy and David A. Patterson
//
//===----------------------------------------------------------------------===//
// Get the target-independent interfaces which we are implementing...
//
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// DLX supported processors.
//===----------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
def : Proc<"generic", []>;
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "DLXRegisterInfo.td"
//===----------------------------------------------------------------------===//
// Calling Convention Description
//===----------------------------------------------------------------------===//
include "DLXCallingConv.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "DLXInstrInfo.td"
def DLXInstrInfo : InstrInfo {}
//===----------------------------------------------------------------------===//
// Target Declaration
//===----------------------------------------------------------------------===//
def DLX : Target {
let InstructionSet = DLXInstrInfo;
}
** DLXRegisterInfo.td *********************************************************
//===- DLX.td - DLX Register definition ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// The register info for the DLX RISC processor architecture
//
//===----------------------------------------------------------------------===//
class DLXReg<string n> : Register<n> {
field bits<5> Num;
let Namespace = "DLX";
}
// DLXR - One of the 32 32-bit general-purpose registers
class DLXR<bits<5> num, string n> : DLXReg<n> {
let Num = num;
}
// General-purpose registers
def R0 : DLXR< 0, "r0">, DwarfRegNum<[0]>;
def R1 : DLXR< 1, "r1">, DwarfRegNum<[1]>;
def R2 : DLXR< 2, "r2">, DwarfRegNum<[2]>;
def R3 : DLXR< 3, "r3">, DwarfRegNum<[3]>;
def R4 : DLXR< 4, "r4">, DwarfRegNum<[4]>;
def R5 : DLXR< 5, "r5">, DwarfRegNum<[5]>;
def R6 : DLXR< 6, "r6">, DwarfRegNum<[6]>;
def R7 : DLXR< 7, "r7">, DwarfRegNum<[7]>;
def R8 : DLXR< 8, "r8">, DwarfRegNum<[8]>;
def R9 : DLXR< 9, "r9">, DwarfRegNum<[9]>;
def R10 : DLXR<10, "r10">, DwarfRegNum<[10]>;
def R11 : DLXR<11, "r11">, DwarfRegNum<[11]>;
def R12 : DLXR<12, "r12">, DwarfRegNum<[12]>;
def R13 : DLXR<13, "r13">, DwarfRegNum<[13]>;
def R14 : DLXR<14, "r14">, DwarfRegNum<[14]>;
def R15 : DLXR<15, "r15">, DwarfRegNum<[15]>;
def R16 : DLXR<16, "r16">, DwarfRegNum<[16]>;
def R17 : DLXR<17, "r17">, DwarfRegNum<[17]>;
def R18 : DLXR<18, "r18">, DwarfRegNum<[18]>;
def R19 : DLXR<19, "r19">, DwarfRegNum<[19]>;
def R20 : DLXR<20, "r20">, DwarfRegNum<[20]>;
def R21 : DLXR<21, "r21">, DwarfRegNum<[21]>;
def R22 : DLXR<22, "r22">, DwarfRegNum<[22]>;
def R23 : DLXR<23, "r23">, DwarfRegNum<[23]>;
def R24 : DLXR<24, "r24">, DwarfRegNum<[24]>;
def R25 : DLXR<25, "r25">, DwarfRegNum<[25]>;
def R26 : DLXR<26, "r26">, DwarfRegNum<[26]>;
def R27 : DLXR<27, "r27">, DwarfRegNum<[27]>;
def R28 : DLXR<28, "r28">, DwarfRegNum<[28]>;
def R29 : DLXR<29, "r29">, DwarfRegNum<[29]>;
def R30 : DLXR<30, "r30">, DwarfRegNum<[30]>;
def R31 : DLXR<31, "r31">, DwarfRegNum<[31]>;
// Register classes
def DLXRegs : RegisterClass<"DLX", [i32], 32,
// Volatile
[R0, R1, R2, R3, R4, R5, R6, R7,
R8, R9, R10, R11, R12, R13, R14, R15,
R16, R17, R18, R19, R20, R21, R22, R23,
R24, R25, R26, R27, R28, R29, R30, R31]>
{
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
DLXRegsClass::iterator
DLXRegsClass::allocation_order_end(const MachineFunction &MF) const {
return begin() + 1; // dont allocate r0, it always contains zero
}
DLXRegsClass::iterator
DLXRegsClass::allocation_order_end(const MachineFunction &MF) const {
return end() - 1; // dont allocate r31, its the link register
}
}];
}
** DLXInstrInfo.td *********************************************************
//===- DLX.td - DLX Instruction definition ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// The Instructions for the DLX RISC processor architecture
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
include "DLXInstrFormats.td"
// arithmetic instructions
defm ADD : RegisterImmediateFormat<"add", 0b001000, add>;
defm DIV : RegisterImmediateFormat<"div", 0b001001, udiv>;
defm MUL : RegisterImmediateFormat<"mul", 0b001011, mul>;
defm SUB : RegisterImmediateFormat<"sub", 0b001010, sub>;
// logical instructions
defm AND : RegisterImmediateFormat<"and", 0b001100, and>;
defm OR : RegisterImmediateFormat<"or", 0b001101, or>;
defm XOR : RegisterImmediateFormat<"xor", 0b001110, xor>;
// conditional instructions
/* ??? whats the format for the SDNode I need?
defm SEQ : RegisterImmediateFormat<"seq", 0b011000, icmp eq
i32>;
defm SNE : RegisterImmediateFormat<"sne", 0b011001, icmp ne
i32>;
defm SGE : RegisterImmediateFormat<"sge", 0b011101, icmp uge
i32>;
defm SGT : RegisterImmediateFormat<"sgt", 0b011011, icmp ugt
i32>;
defm SLE : RegisterImmediateFormat<"sle", 0b011100, icmp ule
i32>;
defm SLT : RegisterImmediateFormat<"slt", 0b011010, icmp ult
i32>;
*/
// memory access instructions
def SWri : ImmediateFormat <0b101010, (outs), (ins DLXRegs:$a, DLXRegs:$b,
i16imm:$c),
!strconcat("sw", "$c($a), $b"),
[/* ??? what goes here? */]>;
def LWri : ImmediateFormat <0b100010, (outs DLXRegs:$dst), (ins i32imm:$b,
i16imm:$c),
!strconcat("lw", "$dst, $c($b)"),
[/* ??? what goes here? */]>;
// load immediate
def LLOri : ImmediateFormat <0b110001, (outs DLXRegs:$dst), (ins i32imm:$b),
!strconcat("llo", "$dst, $b"),
[(set DLXRegs:$dst, (lo16 imm16:$b))]>;
def LHIri : ImmediateFormat <0b110000, (outs DLXRegs:$dst), (ins i32imm:$b),
!strconcat("llo", "$dst, $b"),
[(set DLXRegs:$dst, (hi16 imm16:$b))]>;
** DLXInstrInfo.td *********************************************************
//===- DLX.td - DLX Calling Convention definition ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// The calling convention for the DLX RISC processor architecture
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// DLX Return Value Calling Convention
//===----------------------------------------------------------------------===//
def RetCC_DLX : CallingConv<[
// i32 is returned in register R1
CCIfType<[i32], CCAssignToReg<[R1]>>
]>;
//===----------------------------------------------------------------------===//
// DLX Argument Calling Conventions
//===----------------------------------------------------------------------===//
def CC_DLX : CallingConv<[
// The first 6 arguments are passed in registers
CCIfType<[i32], CCAssignToReg<[R1, R2, R3, R4, R5, R6]>>,
// Stack slots are 4 bytes in size and 4-byte aligned.
CCIfType<[i32], CCAssignToStack<4, 4>>
]>;
