search for: chesterfield

When I run lighttpd 1.4.10 [on Mac OS X] the socket file is called ''fcgi.socket-'', versus ''fcgi.socket-0'' that I get under 1.4.8. Further, when the FCGI daemon quits, the file does not get deleted, and I cannot restart my Rails app until I manually remove it. Can anyone confirm before I raise a bug at lighttpd.net?

Hi everyone! I have 2 hosts + 1 ISCSI device. I want to create a shared storage repository and both hosts use together. I wont use NFS. prepared sr: xe sr-create host-uuid=xxx content-type=user name-label=NAS1 shared=true type=iscsi device-config:target=xxxx device-config:targetIQN=xxxx hosts see the iscsi device: scsi4 : iSCSI Initiator over TCP/IP scsi 4:0:0:0: Direct-Access NAS

Hi, Hexagon has a MIR pass for detecting loops that map onto hardware support. I think a similar approach would be viable for my target but am put off by the complexity of determining whether a given loop is legal to transform. Instead, I would like to pass the responsibility for determining legality onto the C programmer who is assumed sufficiently familiar with the architecture. I think this

...features might people want in it? To begin, the program will only be able to do things that can be done straight through the existing command line tools (net, smbpasswd, etc.). Thoughts, questions, comments? -- Andrew Gaffney System Administrator Skyline Aeronautics, LLC. 776 North Bell Avenue Chesterfield, MO 63005 636-357-1548

...converts to two <2 x i32> => <2 x i31> stores on a target with <2 x i32> legal but would not be split if <4 x i32> were declared legal. Thanks Jon On Fri, Sep 15, 2017 at 7:41 PM, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 9/15/2017 11:30 AM, Jon Chesterfield wrote: > >> Interesting, thank you. I expected both answers to be "unchanged" so was >> surprised by the zero extend in the legaliser. >> >> The motivation here is that it's faster for us to load N bytes, apply >> whatever masks are necessary to reprod...

What should a well behaved back end do with a load or store with alignment less than the natural alignment of the type? I believe C++ considers such access to be UB. I'm not sure what the IR semantics are. I think my options are: - Delete the operation / use undef - Lower as if it is naturally aligned - Lower via inefficient code that assumes align 1 Thanks, Jon -------------- next part

Taking the address of a function inhibits optimisations for that function. Essentially any ABI changes are unavailable if we can't adjust the call site to match. The case of interest here is when a given function is called directly and indirectly, and we don't want the latter to impose a cost on the former. One approach to avoid the ABI constraint cost is to extract/outline the body of an

Video of the Chicago RailsConf keynotes are now online. At least two of them, anyway. So far Martin Fowler''s (Chief Scientist from ThoughWorks) and Dave Thomas'' (author of Pragmattic Programmer and Programming Ruby among others) can be found at blog.scribestudio.com . You can find the general release schedule of the other speakers here:

...earch-and-development/jobid6130734-r-programmer-jobs Please apply if you are passionate about building R culture and infrastructure. . . .. . ... . ... . .. . . ... . ... . . . .. .. .... .. . ... . Barrett Foat, PhD Genome Data Analytics Team Lead Monsanto Company 700 Chesterfield Parkway West Chesterfield, MO 63017 636-737-4366 This e-mail message may contain privileged and/or confidential information, and is intended to be received only by persons entitled to receive such information. If you have received this e-mail in error, please notify the sender immediately. Please...

I would like to specialise build_vector for the case when one of the operands is undefined. How do I describe this? This is looking for an analog of specialisations like: def : Pat <v2i32 (build_vector i32:$x, (i32 0)),...>; but for an undefined, rather than zero, value. I can work around my ignorance in performDAGCombine but would prefer to add to the existing pattern matching. Thanks,

For example, truncating store of an i32 to i6. My assumption was that this should write the low six bits of the i32 to somewhere in memory. Should the top 24 bits of a corresponding 32 bit region of memory be unchanged, zero, undefined? Should the two bits that would round the i6 up to a byte be preserved, zero, undefined? I can't write six bits directly so am trying to determine what set

SelectionDAG's computeKnownBits has no case for ConstantFP, e.g. Known.ones = cast <ConstantFPSDNode>(Op)->getValueAFP ().bitcastToAPInt (); I can't easily override this in target specific code. Can anyone see an issue with submitting the patch to upstream? Suggestions for an in tree target that could trigger this would be very welcome. Cheers -------------- next part

On 9/15/2017 5:49 AM, Jon Chesterfield via llvm-dev wrote: > For example, truncating store of an i32 to i6. My assumption was that > this should write the low six bits of the i32 to somewhere in memory. > > Should the top 24 bits of a corresponding 32 bit region of memory be > unchanged, zero,  undefined? Unchanged. &...

On 09/15/2017 10:55 AM, Friedman, Eli via llvm-dev wrote: > On 9/15/2017 5:49 AM, Jon Chesterfield via llvm-dev wrote: >> For example, truncating store of an i32 to i6. My assumption was that this should write the low six bits of the i32 to somewhere in memory. >> >> Should the top 24 bits of a corresponding 32 bit region of memory be unchanged, zero, undefined? > > Unc...

Hi Jon, Job postings are ok on the llvm mailing list if and only if they are related to LLVM somehow. Please clarify if this is the case - or if not, please refrain from future posts. Thanks! -Chris > On Apr 12, 2018, at 3:11 AM, Jon Chesterfield via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Graphcore is a well funded startup that is developing a new processor architecture for accelerating machine-learning applications. We are looking for talented engineers to build world-class development tools that fully exploit the co...

There was a GSoC project in 2016, final report at https://docs.google.com/document/d/1v-R7gB7Or4bPn0LW7d-yb1yla8jK3DVmTJNFVNYNu6k Google doesn't show a lot of activity since. Has anyone taken this work further / put it near production? I'm interested in removing register spills around functions that are known to not clobber said registers. Thanks! Jon -------------- next part

...T::i8, MemVT should be MVT::i1 else getLoad - Elena From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Monday, September 18, 2017 13:40 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists.llvm.org Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' um... In order to reproduce the issue, we need to add 'i1' register class and avoid all vector register class on TargetLowering cl...

Graphcore is a well funded startup that is developing a new processor architecture for accelerating machine-learning applications. We are looking for talented engineers to build world-class development tools that fully exploit the computational capabilities of our architecture. Multiple roles are available - if you enjoy hacking on compilers, debuggers or linkers we would like to speak to you.

On Thu, Feb 6, 2020 at 9:15 AM James Henderson <jh7370.2008 at my.bristol.ac.uk> wrote: > > On Thu, 6 Feb 2020 at 00:24, Jon Chesterfield via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> This doesn't sound right. GNU binutils have a large quantity of legacy >> cruft, not least the redundancy between tools like readelf and objdump >> which are capable of doing the same task in exchange for dif...

...case. It will allow us to debug and fix the problem. Thanks - Elena From: JinGu [mailto:jingu at codeplay.com] Sent: Saturday, September 16, 2017 00:38 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists.llvm.org Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Hi Elena, Thanks for your response. The store is ok but the extending load generates assertion after the store because MemVT is i8 and VT...