search for: blt

...l.thibault@eu.citrix.com> diff -r 067d8f19e78a tools/ioemu/hw/xenfb.c --- a/tools/ioemu/hw/xenfb.c Thu Feb 28 13:55:37 2008 +0000 +++ b/tools/ioemu/hw/xenfb.c Fri Feb 29 15:25:17 2008 +0000 @@ -1072,7 +1072,7 @@ /* A convenient function for munging pixels between different depths */ #define BLT(SRC_T,DST_T,RLS,GLS,BLS,RRS,GRS,BRS,RM,GM,BM) \ - for (line = y ; line < h ; line++) { \ + for (line = y ; line < (y+h) ; line++) { \ SRC_T *src = (SRC_T *)(xenfb->pixels \...

.... Therefore, the git log is quite long and there are multiple changes, fixes and enhancements. The main changes are: - ARMv6 - Many fast paths implementations were added - PPC64/PPC64LE - Fix all outstanding bugs and add many fast paths implementations using vmx - Major enhancements to lowlevel-blt-bench utility - A couple of fixes and enhancements to mmx code As I mentioned above, many more fixes and improvements to various parts of the code. Please test, and report bugs to the mailing list at pixman at lists.freedesktop.org. To anyone interested, I would like to note that I intend to p...

...test: Fix the win32 build test: Fix fence-image-self-test on Mac mmx: Improve detection of support for "K" constraint Ben Avison (27): ARMv6: Fix indentation in the composite macros ARMv6: remove 1 instr per row in generate_composite_function lowlevel-blt-bench: over_reverse_n_8888 needs solid source lowlevel-blt-bench: add in_reverse_8888_8888 test ARMv6: Add fast path for over_reverse_n_8888 ARMv6: Support for very variable-hungry composite operations ARMv6: Add fast path for over_n_8888_8888_ca ARMv6: Add fast p...

...B @003F96D8, ID#3: Live Ins: %D0 %D1 Predecessors according to CFG: 01916530 (#1) 01916C10 (#4) %D2 = MOVE_imm_dr32 2 %D1 = ADDQ_dr_dr32_1 %D1<kill> %D3 = ASR_imm_dr32 %D0, 1 CMP_dr_dr32 %D0<kill>, %D2<kill> %D0<dead> = SLT BLT mbb<bb5.bb9_crit_edge,01915940> Successors according to CFG: 01915940 (#5) 01916C10 (#4) bb5.bb5_crit_edge: 01916C10, LLVM BB @003FC060, ID#4: Live Ins: %D1 %D3 Predecessors according to CFG: 01916700 (#3) BRA mbb<bb5,01916700> %D0 = MOVE_dr_dr32 %D3<kill>...

...end as a template, fixing > things as I go. > > Now I've run into branches and I have a crash I don't really > understand. Here's the sample IR I'm running llc on to generate > assembly: > <snip> > llc crashes at this point because the target branch of the BLT (branch > if lower than) has gone away. On my win32 box it's filled with > 0xfeeefeee (deleted data). > > I've verified that the block is actually removed by the branch > folding, but for some reason this poor BLT instruction never hears > about that. What can I do to fix...

Editing subject line to reflect current status. On 1/26/06, Nilesh Londhe <lvnilesh@gmail.com> wrote: > Since T616 is not answering (and incoming calls are going to Cingular > voicemail after 30 sec,) I suspect the problem focus area is... > > > -- Executing Answer("BLT/T616", "") in new stack > > Is http://www.thetechguide.com/howto/asterisk/bluetoothfiles.tar.gz > tar xzf bluetoothfiles.tar.gz the latest source (r40?) > > On 1/26/06, Nilesh Londhe <lvnilesh@gmail.com> wrote: > > Here are my findings with my experiment us...

...@ %for.body.91 @ =>This Inner Loop Header: Depth=1 ldr r0, [r5] mov r1, r8 add r0, r0, r7 vldr s0, [r0] mov r0, r6 vcvt.f64.f32 d0, s0 vmov r2, r3, d0 bl fprintf cmp r0, #0 blt .LBB4_25 @ BB#20: @ %for.cond.89 @ in Loop: Header=BB4_19 Depth=1 ldr r0, .LCPI4_2 add r4, r4, #1 add r7, r7, #4 ldr r0, [r0] cmp r4, r0 blt .LBB4_19 There are no other basic bl...

Howdy, <---stuff deleted -----> Basically the architecture I want to compile to (SABRE) RISC does not support a conditional branch or a select instruction. It supports explicit branches of the form. blt %a, %b, imm // branch on less than iff %a < %b then pc = pc + imm So there are various branch instructions like .... ble, beq, bne, blt, bltu and bleu (unsigned) Im just slightly confused as to the distinction between expand and custom, and when it becomes appropriate to use custom over expa...

...Inner Loop Header: Depth=1 > ldr r0, [r5] > mov r1, r8 > add r0, r0, r7 > vldr s0, [r0] > mov r0, r6 > vcvt.f64.f32 d0, s0 > vmov r2, r3, d0 > bl fprintf > cmp r0, #0 > blt .LBB4_25 > @ BB#20: @ %for.cond.89 > @ in Loop: Header=BB4_19 Depth=1 > ldr r0, .LCPI4_2 > add r4, r4, #1 > add r7, r7, #4 > ldr r0, [r0] > cmp r4, r0...

...andR transform (e.g. rotation) is in effect. https://bugs.freedesktop.org/show_bug.cgi?id=52255 https://bugs.freedesktop.org/show_bug.cgi?id=56608 Chris Wilson (16): sna: Use a single execobject flag to mark read/write domains sna: Disable shadow tracking upon regen sna/blt: Avoid clobbering common state before converting to a BLT sna/gen5+: Disable max-vbo address sna/gen6+: Override PTE cacheability bits for reads sna/g4x: Emit the flush prior to changing pipelined state sna/g4x: Remove the flush before the pipelined pointer changes sna...

...http://cairographics.org/snapshots/pixman-0.29.4.tar.gz.sha1.asc (signed by S?ren Sandmann Pedersen <soren.sandmann at gmail.com>) Git: git://git.freedesktop.org/git/pixman tag: pixman-0.29.4 Log: Behdad Esfahbod (1): Remove unused macro Ben Avison (1): Fix to lowlevel-blt-bench Nemanja Lukic (11): MIPS: DSPr2: Added more fast-paths for OVER operation: MIPS: DSPr2: Added more fast-paths for SRC operation: MIPS: DSPr2: Fix bug in over_n_8888_8888_ca/over_n_8888_0565_ca routines MIPS: DSPr2: Added over_8888_8888 nearest neighbor fast path...

...%28 = load volatile i32* inttoptr (i64 2149581832 to i32*), align 8 %29 = icmp slt i32 %28, 0 br i1 %29, label %27, label %loop.exit loop.exit: ; preds = %27 llc will generate following MIPS code, $BB0_1: lui $3, 32800 ori $3, $3, 1032 lw $3, 0($3) bltz $3, $BB0_1 nop # BB#2: The two operation lui and ori which are used to calculate memory address actually are loop invariants. They supposed to be moved out of the loop. I thought it might be a limitation of the MIPS backend. Then I tried the ARM backend, .LBB1_1: ldr r2, .LCPI1_2 ldr...

Back in the day, we called this a BLT (block transfer, pronouced 'blit') for the PDP-10 instruction of that name. You can do this by assigning the first value, then do an overlapping memcpy to fill in the rest. There's probably something clever you can do with vector instructions too, in many cases. --paulr From: llvm-dev...

...16: arg 4 */ ++ move.l %d3, -(%sp) /* push d3 (callee saved) */ ++ move.l 24(%sp), %d3 /* orig.sp+12: arg 3 */ ++ move.l %d2, %a1 /* save d2 (callee saved) in a1 */ ++ move.l 20(%sp), %d2 /* orig.sp+8: arg 2 */ ++ move.l 16(%sp), %d1 /* orig.sp+4: arg 1 */ + trap #0 +- cmpi.l #-4095, %d0 +- blt.l 1f ++ move.l %a1, %d2 /* restore d2 from a1 (scratch) */ ++ move.l (%sp)+, %d3 /* pop d3..d5, see above */ ++ move.l (%sp)+, %d4 ++ move.l (%sp)+, %d5 ++ ++ /* syscall is done, result in %d0, registers are restored */ ++ .globl __syscall_checkandout ++__syscall_checkandout: ++ /* now check for...

...el %ret_true ubyte 98, label %ret_true ] Unfortunately, this generates really weird code on the LLVM 1.6 PowerPC backend: LBB_matches_1: ; regex6 lbz r4, 0(r3) LBB_matches_2: ; NodeBlock rlwinm r5, r4, 0, 24, 31 cmplwi cr0, r5, 98 blt cr0, LBB_matches_4 ; LeafBlock LBB_matches_3: ; LeafBlock1 rlwinm r4, r4, 0, 24, 31 cmpwi cr0, r4, 98 beq cr0, LBB_matches_8 ; ret_true b LBB_matches_5 ; NewDefault LBB_matches_4: ; LeafBlock rlwinm r4, r4, 0, 24, 31 cmpwi cr0, r4, 97...

...to a .o with -O2 -march=RV32IC we get (just looking at foo) 00000000 <foo>: 0: 1141 addi sp,sp,-16 2: c422 sw s0,8(sp) 4: c606 sw ra,12(sp) 6: 06300793 li a5,99 a: 842a mv s0,a0 c: 00a7cb63 blt a5,a0,22 <.L2> 10: 85aa mv a1,a0 12: 00000537 lui a0,0x0 16: 00050513 mv a0,a0 1a: 00000317 auipc t1,0x0 1e: 000300e7 jalr t1 00000022 <.L2>: 22: 40b2 lw ra,12(sp) 24: 8522 mv a0,s0...

...terisk-1.2.0 on FC3. When I try to make a call to my home through the channel my phone shows calling but my home phone never rings. I get this on screen: == Spawn extension (outgoing, 3234600, 2) exited non-zero on 'SIP/2299-9131' -- Executing Dial("SIP/2299-7743", "BLT/John/3541107") in new stack [AG] John < ATD3541107; -- Called John [AG] John > OK [AG] John > +CIEV: 3,2 [AG] John > +CIEV: 4,2 [AG] John > ERROR [AG] John > +CIEV: 1,0 [AG] John < ATH [AG] John < AT+CHUP ==...

I've tagged a release for libdrm 2.4.23 principally to expose the new kernel parameters for BLT support on SandyBridge and relaxed fencing which are needed to build the next release of xf86-video-intel. However, I'm lacking sufficient privileges to actually upload the tarballs myself at the moment, so you'll have to make do with the git tag! -Chris Adam Jackson (1): s/drmStrdu...

...t;> things as I go. >> >> Now I've run into branches and I have a crash I don't really >> understand. Here's the sample IR I'm running llc on to generate >> assembly: >> <snip> >> llc crashes at this point because the target branch of the BLT >> (branch >> if lower than) has gone away. On my win32 box it's filled with >> 0xfeeefeee (deleted data). >> >> I've verified that the block is actually removed by the branch >> folding, but for some reason this poor BLT instruction never hears >&gt...

...anage to make a phone call from a soft phone to a GSM network. However, i have an audio problem. The soft phone can be heart by the GSM costumer but the voice in Xlite is not transmitted to the GSM. In asterisk all i got is the next lines: -- Executing Dial("SIP/Jack-081e39b0", "BLT/nokia/07863342772") in new stack [AG] nokia < ATD07863342772; -- Called nokia [AG] nokia > OK [AG] nokia > +CIEV: 3,2 [AG] nokia > +CIEV: 4,2 [AG] nokia > +CIEV: 3,3 -- BLT/nokia is ringing [AG] nokia > +CIEV: 4,3 [AG] nokia > +CI...