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Clang warns several times when building for 32-bit ARM along the lines of: drivers/vdpa/mlx5/net/mlx5_vnet.c:1462:31: warning: shift count >= width of type [-Wshift-count-overflow] ndev->mvdev.mlx_features |= BIT(VIRTIO_F_VERSION_1); ^~~~~~~~~~~~~~~~~~~~~~~ This is related to the B...

Clang warns several times when building for 32-bit ARM along the lines of: drivers/vdpa/mlx5/net/mlx5_vnet.c:1462:31: warning: shift count >= width of type [-Wshift-count-overflow] ndev->mvdev.mlx_features |= BIT(VIRTIO_F_VERSION_1); ^~~~~~~~~~~~~~~~~~~~~~~ This is related to the B...

...s with that particular curve. Printing certs and verifying certs against keys is panning out too, comparing md5 hashes also no errors. So why would openssl not accept (limit) keys is has generated and verified with no error? [ openssl ecparam -list_curves ] ? secp112r1 : SECG/WTLS curve over a 112 bit prime field ? secp112r2 : SECG curve over a 112 bit prime field ? secp128r1 : SECG curve over a 128 bit prime field ? secp128r2 : SECG curve over a 128 bit prime field ? secp160k1 : SECG curve over a 160 bit prime field ? secp160r1 : SECG curve over a 160 bit prime field ? secp160r2 : SECG/WTLS cur...

...illier for architectures with base page size >4k. I completely agree with you that we should be able to pass a hugepage as a single chunk. Also we shouldn't assume that host and guest have the same page size. I think we can come up with a scheme that actually lets us encode that into a 64-bit word, something like this: bit 0 clear => bits 1-11 encode a page count, bits 12-63 encode a PFN, page size 4k. bit 0 set, bit 1 clear => bits 2-12 encode a page count, bits 13-63 encode a PFN, page size 8k bits 0+1 set, bit 2 clear => bits 3-13 for page count, bits 14-63 for PFN, page si...

...iversity\ProgettoInterdisciplinare\speex-1.2rc1\speex-1.2rc1\symbian\WINSCW.make" LIBRARY VERBOSE=-s make -s -r -f "\S60\devices\S60_3rd_FP2_SDK_v1.1\EPOC32\BUILD\Users\Maurizio\University\ProgettoInterdisciplinare\speex-1.2rc1\speex-1.2rc1\symbian\SPEEX\WINSCW\SPEEX.WINSCW" LIBRARY bits.c ..\libspeex\bits.c:48: declaration syntax error ..\libspeex\bits.c:49: declaration syntax error ..\libspeex\bits.c:54: declaration syntax error ..\libspeex\bits.c:56: declaration syntax error ..\libspeex\bits.c:58: identifier 'speex_bits_reset(struct SpeexBits *)' redeclared ..\libspeex\...

...g within tc. But alas, I am having an issue I know I should not be having. I am trying to filter all IRC traffic on my network so that it neither consumes large amounts of band width nor gets to little band width. I originally wanted to filter just ports 6660-6669 but quickly realized that the bit masking wouldn''t allow for a single rule to cover them, so I opted instead to filter ports 6656-66671 which would give me the use of all 4 bits in that range. For reference, 6656 = 0x1a00, 6671 = 0x1a0f. As such, I have the following rules in my setup: eth0 egress to the internet (eth0...

Hello FLAC list. As far as I know 24 bit FLAC support is broken. It often doesn't compress the audio at all, but instead stores the chunks as verbatim type (although the FLAC format supports 24 bit). Perhaps this is fixed? If so, do let me know. I agree that perhaps 32 bit float/pcm isn't entirely necessary when it comes to sto...

I am trying to prototype a back end for a new processor. It has a 64-bit datapath, so all registers are 64 bits and load instructions always extend to 64 bits. But the type 'int' is 32 bits, and arithmetic instructions have variants that operate on only the lower 32 bits of each register. So for a basic 'a = b + c' example, we get %0 = load i32, i32*...

...> >>>>>>> facing [ no shared cipher ] error with EC private keys. > >>>>>> the client connecting to your instance has to support ecdsa > >>>>>> > >>>>>> > >>>>> It does - Thunderbird 60.0b10 (64-bit) > >>>>> > >>>>> [ security.ssl3.ecdhe_ecdsa_aes_256_gcm_sha384;true ] > >>>>> > >>>>> It seems there is a difference between the private key (rsa vs. ecc -> > >>>>> SSL_CTX?) used for the certificate signi...

...ns diff --git a/libswfdec/swfdec_tag.c b/libswfdec/swfdec_tag.c index a556e19..ef1db99 100644 --- a/libswfdec/swfdec_tag.c +++ b/libswfdec/swfdec_tag.c @@ -387,43 +387,56 @@ swfdec_button_append_content (SwfdecButt static int tag_func_define_button_2 (SwfdecSwfDecoder * s, guint tag) { - SwfdecBits *bits = &s->b; - int id; - int flags; - int offset; + SwfdecBits bits; + int id, reserved; + guint length; SwfdecButton *button; char *script_name; - id = swfdec_bits_get_u16 (bits); + id = swfdec_bits_get_u16 (&s->b); button = swfdec_swf_decoder_create_character (...

...e\speex\symbian\ library winscw make -r -f "\Symbian\9.1\S60_3rd_MR\EPOC32\BUILD\Symbian\Carbide\workspace\speex\symbian\WINSCW.make" LIBRARY VERBOSE=-s User break, cancelled... make[1]: *** [\Symbian\9.1\S60_3rd_MR\EPOC32\BUILD\Symbian\Carbide\workspace\speex\symbian\SPEEX\WINSCW\UDEB\bits.o] Error 2 make: *** [LIBRARYSPEEX] Error 2 make -s -r -f "\Symbian\9.1\S60_3rd_MR\EPOC32\BUILD\Symbian\Carbide\workspace\speex\symbian\SPEEX\WINSCW\SPEEX.WINSCW" LIBRARY bits.c ..\libspeex\bits.c:48: declaration syntax error ..\libspeex\bits.c:49: declaration syntax error ..\libspeex\b...

...ffered to the host via a base PFN (i.e. the start PFN of > > > those physically continuous pages) and the size (i.e. the total > > > number of the pages). A normal chunk is formated as below: > > > ----------------------------------------------- > > > | Base (52 bit) | Size (12 bit)| > > > ----------------------------------------------- > > > For large size chunks, an extended chunk format is used: > > > ----------------------------------------------- > > > | Base (64 bit) | > &...

...ffered to the host via a base PFN (i.e. the start PFN of > > > those physically continuous pages) and the size (i.e. the total > > > number of the pages). A normal chunk is formated as below: > > > ----------------------------------------------- > > > | Base (52 bit) | Size (12 bit)| > > > ----------------------------------------------- > > > For large size chunks, an extended chunk format is used: > > > ----------------------------------------------- > > > | Base (64 bit) | > &...

On 8/21/20 3:50 PM, Nathan Chancellor wrote: > Clang warns several times when building for 32-bit ARM along the lines > of: > > drivers/vdpa/mlx5/net/mlx5_vnet.c:1462:31: warning: shift count >= width > of type [-Wshift-count-overflow] > ndev->mvdev.mlx_features |= BIT(VIRTIO_F_VERSION_1); > ^~~~~~~~~~~~~~~~~~~...

...refix. // Where are these prefix names coming from? I can't find any mention of them in the Intel literature. Also, there's this curious table: // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. class OpSize { bit hasOpSizePrefix = 1; } class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class TB { bits<4> Prefix = 1; } class REP { bits<4> Prefix = 2; } class D8 { bits<4> Prefix = 3; } class D9 { bits<4...

...sctl machdep.cpu.brand_string machdep.cpu.brand_string: Intel(R) Core(TM) i5-2415M CPU @ 2.30GHz $ /usr/bin/openssl speed rsa [...] LibreSSL 2.2.7 built on: date not available options:bn(64,64) rc4(ptr,int) des(idx,cisc,16,int) aes(partial) blowfish(idx) compiler: information not available rsa 512 bits 0.000964s 0.000059s 1037.3 16987.1 rsa 1024 bits 0.006052s 0.000271s 165.2 3687.3 rsa 2048 bits 0.040528s 0.001145s 24.7 873.6 rsa 4096 bits 0.278889s 0.004272s 3.6 234.1 $ libressl-2.2.7/apps/openssl speed rsa [...] options:bn(64,64) rc4(16x,int) des(idx,cisc,16,int) aes(p...

Hello Ralph, > Likewise opus_encode() takes 16 bit samples, so you need to extend each > sample from an 8 bit source before encoding. Two questions 1. In opusenc.c which API does the extending the 8-bit to 16-bit? 2. If that is the case then how will 24 bit PCM sample work? Regards Amit On Thu, Jan 7, 2016 at 12:21 PM, Ralph Giles <giles a...

libswfdec/swfdec_bits.c | 81 +++++++++++++++++++++++++++++----------------- libswfdec/swfdec_bits.h | 1 libswfdec/swfdec_sprite.c | 6 --- libswfdec/swfdec_tag.c | 12 ------ 4 files changed, 55 insertions(+), 45 deletions(-) New commits: diff-tree 493905baa1c07054276adb078f086e7ca4acc26b (from par...

...gdi32/mfdrv commands config.status: executing dlls/kernel32/nls commands config.status: executing dlls/user32/resources commands config.status: executing dlls/wineps.drv/data commands config.status: executing include/wine commands config.status: executing Makefile commands configure: libxcursor 32-bit development files not found, the Xcursor extension won't be supported. configure: libxi 32-bit development files not found, the Xinput extension won't be supported. configure: libXxf86vm 32-bit development files not found, XFree86 Vidmode won't be supported. configure: libxrandr 32-bit...

...;s style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach, I propose to change LLVM/clang by adding: + a metadata 'targetflags' in LLVM atomic IR to pass this target-specific memory model hint + one extra target flag in AtomicSD...