search for: arminstrthumb2

Hi Artur, The Thumb2 target (in lib/Targets/ARM/ARMInstrThumb2.td) materializes a 32-bit constant by a two-instruction sequence to load the low and high half-words. It's not pretty, but it works. The pattern is at the bottom of the file. Regards, -Jim On Oct 6, 2009, at 5:10 AM, Artur Pietrek wrote: > Hi all, > I'm working on my own back...

...ld know about them too, not just the MC layer, so this is even more of a hack," - and he suggested instead converting every instruction that takes an rGPR operand into a multiclass of two instructions, one predicated on HasV8Ops, and the other on its inverse. This isn't practical, however: ARMInstrThumb2.td specifies several hundred individual encodings, InstAliases and match patterns that use rGPR, and all these would need to be manually duplicated. Right now, we're trying to come up with a more sensible approach, and perhaps one that could be useful for other targets as well. Any sugg...

...sland entries into .rodata (i.e. skip constant island pass). In the thumb2 case, the expected match- ARMISD::Wrapper, which is supposed to morphed to a t2MOVi32imm never happens: I've placed all the expected patterns to match tconstpool and (hopefully) turned on the correct Requires flag in the ARMInstrThumb2.td in all the places where ARMWrapper tconstpool occurs. However, the expected match does not occur and I am at a loss to explain it. I suppose there are several things that could be broken: 1. There is a bug in the patterns I specified in the .td file 2. There is some hardcoded glue in ARM...

Hi all,I'm working on my own backend for a custom CPU. I have defined paired registers for 64bit operations, however to set a 64bit paired register with 64bit immediate I have to set each register in that pair separately with the higher and the lower 32bits of the immediate. Could anyone give me an advice how to describe it in *InstructionInfo.td or point me to something similar in the LLVM

Hi Kurt, The assembly parser doesn't (yet) handle these, you're right. Currently, the MRS instruction is split into two variants in the ARMInstrThumb2.td file, t2MRS and t2MRSsys, one for the user mode version reading cpsr and one for the system mode version reading spsr. MSR, by contrast, has a custom parse method for the mask operand since it's a bit more complex than an either/or. You'll likely want to merge the two MRS variants into...

...August 2011 18:06 > To: Kurt Lidl > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] cortex-m{3,4} special registers > > Hi Kurt, > > The assembly parser doesn't (yet) handle these, you're right. Currently, > the MRS instruction is split into two variants in the ARMInstrThumb2.td > file, t2MRS and t2MRSsys, one for the user mode version reading cpsr and > one for the system mode version reading spsr. MSR, by contrast, has a > custom parse method for the mask operand since it's a bit more complex than > an either/or. > > You'll likely want to me...

...ss<"ARM", [i32], 32, (add R6)>; 2) modify the RC used in the addr_offset_none addressing mode in ARMInstrInfo.td around line 947 to: let MIOperandInfo = (ops PTRRC:$base); (this is used by the t2LDR_POST instruction) 3) and likewise modify the t2addrmode_imm12 addressing mode in ARMInstrThumb2.td around line 151 to: let MIOperandInfo = (ops PTRRC:$base, i32imm:$offsimm); (used by the load/store instructions) then compile with -O3 and done :) In addition, I've attached the debugging info generated by the regalloc for the Thumb2 target. The main difference of the debug output using m...

I was attempting to compile some code with a recent (r138716) version of llvm/clang, targeting a cortex-m4 processor. And I get an error like this: CC: sched_garbage.c In file included from sched_garbage.c:43: In file included from ./os_internal.h:48: In file included from /p/nuttx/trunk/nuttx/include/sched.h:47: In file included from /p/nuttx/trunk/nuttx/include/nuttx/sched.h:54: In file

...l > > Cc: llvmdev at cs.uiuc.edu > > Subject: Re: [LLVMdev] cortex-m{3,4} special registers > > > > Hi Kurt, > > > > The assembly parser doesn't (yet) handle these, you're right. Currently, > > the MRS instruction is split into two variants in the ARMInstrThumb2.td > > file, t2MRS and t2MRSsys, one for the user mode version reading cpsr and > > one for the system mode version reading spsr. MSR, by contrast, has a > > custom parse method for the mask operand since it's a bit more complex than > > an either/or. > > > &gt...

On Dec 17, 2012, at 8:38 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Hello, > > I'm getting the "LLVM ERROR: ran out of registers during register allocation" error message for an out of tree target I'm developing. This is happening for the following piece of C code: > > struct ss > { > int a; > int b; > int c; > }; > void

Hi, I have a question about the definitions of t2LDRSB and t2LDRSB_PRE in ARMInstrThumb2.td : I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enfor...

Right, I understand that. So why is 0x7FFF matching fine but not 0x8000 both fit in 16 bit? Thanks. On Wed, Feb 15, 2017 at 1:24 PM, Reid Kleckner <rnk at google.com> wrote: > LLVM IR integers have no sign. You can't reliably tell whether an add or > subtract was signed or unsigned when generating code. > > On Wed, Feb 15, 2017 at 10:19 AM, Ryan Taylor via llvm-dev <

...R6)>; > > 2) modify the RC used in the addr_offset_none addressing mode in > ARMInstrInfo.td around line 947 to: > let MIOperandInfo = (ops PTRRC:$base); > (this is used by the t2LDR_POST instruction) > > 3) and likewise modify the t2addrmode_imm12 addressing mode in > ARMInstrThumb2.td around line 151 to: > let MIOperandInfo = (ops PTRRC:$base, i32imm:$offsimm); > (used by the load/store instructions) > > then compile with -O3 and done :) > > In addition, I've attached the debugging info generated by the regalloc > for the Thumb2 target. The main diffe...

Hello, I'm getting the "LLVM ERROR: ran out of registers during register allocation" error message for an out of tree target I'm developing. This is happening for the following piece of C code: struct ss { int a; int b; int c; }; void loop(struct ss *x, struct ss **y, int z) { int i; for (i=0; i<z; ++i) { x->c += y[i]->b; } } The problem relies in