Alexandre Courbot
2014-May-27 04:59 UTC
[Nouveau] [PATCH 0/2] nvc0: support for GK20A (Tegra K1)
The following 2 patches make it possible to run Mesa programs on GK20A (Tegra K1). GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class as well as the same ISA as GK110 (SM35). Taking these differences into account is sufficient to successfully render simple off-screen buffers. Alexandre Courbot (2): nvc0: add GK20A 3D class nvc0: use SM35 ISA with GK20A src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 5 files changed, 20 insertions(+), 6 deletions(-) -- 1.9.3
GK20A is mostly compatible with GK104, but features a new 3D
class. Add it to the relevant header and use it when GK20A is
detected.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
src/gallium/drivers/nouveau/nv_object.xml.h | 1 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h
b/src/gallium/drivers/nouveau/nv_object.xml.h
index 4c93e6564838..0a0e187dc028 100644
--- a/src/gallium/drivers/nouveau/nv_object.xml.h
+++ b/src/gallium/drivers/nouveau/nv_object.xml.h
@@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
#define NVC8_3D_CLASS 0x00009297
#define NVE4_3D_CLASS 0x0000a097
#define NVF0_3D_CLASS 0x0000a197
+#define NVEA_3D_CLASS 0x0000a297
#define GM107_3D_CLASS 0x0000b097
#define NV50_2D_CLASS 0x0000502d
#define NVC0_2D_CLASS 0x0000902d
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index cccfe2bba23d..95e5ef81cd79 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev)
obj_class = NVF0_3D_CLASS;
break;
case 0xe0:
- obj_class = NVE4_3D_CLASS;
+ switch (dev->chipset) {
+ case 0xea:
+ obj_class = NVEA_3D_CLASS;
+ break;
+ default:
+ obj_class = NVE4_3D_CLASS;
+ break;
+ }
break;
case 0xd0:
obj_class = NVC8_3D_CLASS;
--
1.9.3
Alexandre Courbot
2014-May-27 04:59 UTC
[Nouveau] [PATCH 2/2] nvc0: use SM35 ISA with GK20A
GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use
the GK110 path when this chip is detected.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 +
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++----
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index bbb89d97932e..aab857ee7e4f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol
#define NVISA_GF100_CHIPSET_C0 0xc0
#define NVISA_GF100_CHIPSET_D0 0xd0
#define NVISA_GK104_CHIPSET 0xe0
+#define NVISA_GK20A_CHIPSET 0xea
#define NVISA_GK110_CHIPSET 0xf0
#define NVISA_GM107_CHIPSET 0x110
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index b1f76cf80432..f69e6a183e19 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type)
CodeEmitter *
TargetNVC0::getCodeEmitter(Program::Type type)
{
- if (chipset >= NVISA_GK110_CHIPSET)
+ if (chipset >= NVISA_GK20A_CHIPSET)
return createCodeEmitterGK110(type);
return createCodeEmitterNVC0(type);
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 064e7a2c63f9..8212bfd9555e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t
*size) const
{
switch (chipset & ~0xf) {
case 0xe0:
- *code = (const uint32_t *)&gk104_builtin_code[0];
- *size = sizeof(gk104_builtin_code);
- break;
+ if (chipset != NVISA_GK20A_CHIPSET) {
+ *code = (const uint32_t *)&gk104_builtin_code[0];
+ *size = sizeof(gk104_builtin_code);
+ break;
+ }
+ /* fall-through for GK20A */
case 0xf0:
case 0x100:
*code = (const uint32_t *)&gk110_builtin_code[0];
@@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const
switch (chipset & ~0xf) {
case 0xe0:
- return gk104_builtin_offsets[builtin];
+ if (chipset != NVISA_GK20A_CHIPSET)
+ return gk104_builtin_offsets[builtin];
+ /* fall-through for GK20A */
case 0xf0:
case 0x100:
return gk110_builtin_offsets[builtin];
--
1.9.3
On Tue, May 27, 2014 at 12:59 AM, Alexandre Courbot <acourbot at nvidia.com> wrote:> GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use > the GK110 path when this chip is detected. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- > src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- > 3 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > index bbb89d97932e..aab857ee7e4f 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > @@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol > #define NVISA_GF100_CHIPSET_C0 0xc0 > #define NVISA_GF100_CHIPSET_D0 0xd0 > #define NVISA_GK104_CHIPSET 0xe0 > +#define NVISA_GK20A_CHIPSET 0xea > #define NVISA_GK110_CHIPSET 0xf0 > #define NVISA_GM107_CHIPSET 0x110 > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > index b1f76cf80432..f69e6a183e19 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > @@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) > CodeEmitter * > TargetNVC0::getCodeEmitter(Program::Type type) > { > - if (chipset >= NVISA_GK110_CHIPSET) > + if (chipset >= NVISA_GK20A_CHIPSET) > return createCodeEmitterGK110(type); > return createCodeEmitterNVC0(type); > }As mentioned on IRC, you also need to update TargetNVC0::getFileSize to return 255 GPRs, since that value is presumably ISA-specific. You could, at that point, get rid of the GK110_CHIPSET define. Eventually all that stuff needs to be nuked and replaced with an 'isa' property. But you don't have to do that.> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > index 064e7a2c63f9..8212bfd9555e 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > @@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const > { > switch (chipset & ~0xf) { > case 0xe0: > - *code = (const uint32_t *)&gk104_builtin_code[0]; > - *size = sizeof(gk104_builtin_code); > - break; > + if (chipset != NVISA_GK20A_CHIPSET) {You change the code emitter if chipset >= GK20A. Might as well be consistent here and below.> + *code = (const uint32_t *)&gk104_builtin_code[0]; > + *size = sizeof(gk104_builtin_code); > + break; > + } > + /* fall-through for GK20A */ > case 0xf0: > case 0x100: > *code = (const uint32_t *)&gk110_builtin_code[0]; > @@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const > > switch (chipset & ~0xf) { > case 0xe0: > - return gk104_builtin_offsets[builtin]; > + if (chipset != NVISA_GK20A_CHIPSET) > + return gk104_builtin_offsets[builtin]; > + /* fall-through for GK20A */ > case 0xf0: > case 0x100: > return gk110_builtin_offsets[builtin]; > -- > 1.9.3 >
On Tue, May 27, 2014 at 12:59 AM, Alexandre Courbot <acourbot at nvidia.com> wrote:> GK20A is mostly compatible with GK104, but features a new 3D > class. Add it to the relevant header and use it when GK20A is > detected. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > src/gallium/drivers/nouveau/nv_object.xml.h | 1 + > src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h b/src/gallium/drivers/nouveau/nv_object.xml.h > index 4c93e6564838..0a0e187dc028 100644 > --- a/src/gallium/drivers/nouveau/nv_object.xml.h > +++ b/src/gallium/drivers/nouveau/nv_object.xml.h > @@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > #define NVC8_3D_CLASS 0x00009297 > #define NVE4_3D_CLASS 0x0000a097 > #define NVF0_3D_CLASS 0x0000a197 > +#define NVEA_3D_CLASS 0x0000a297 > #define GM107_3D_CLASS 0x0000b097 > #define NV50_2D_CLASS 0x0000502d > #define NVC0_2D_CLASS 0x0000902d > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > index cccfe2bba23d..95e5ef81cd79 100644 > --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > @@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) > obj_class = NVF0_3D_CLASS; > break; > case 0xe0: > - obj_class = NVE4_3D_CLASS; > + switch (dev->chipset) { > + case 0xea: > + obj_class = NVEA_3D_CLASS;Again, would be nice to be consistent with the way you set the ISA... perhaps change this to a >= as well? But I guess the two could be disconnected. Up to you, just thought I'd bring it up.> + break; > + default: > + obj_class = NVE4_3D_CLASS; > + break; > + } > break; > case 0xd0: > obj_class = NVC8_3D_CLASS; > -- > 1.9.3 >
Alexandre Courbot
2014-May-27 07:03 UTC
[Nouveau] [PATCH v2 0/2] nvc0: support for GK20A (Tegra K1)
The following 2 patches make it possible to run Mesa programs on GK20A (Tegra K1). GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class as well as the same ISA as GK110 (SM35). Taking these differences into account is sufficient to successfully render simple off-screen buffers. Changes since v1: - Update TargetNVC0::getFileSize() to return the right number of GPR - Remove definition for unneeded NVISA_GK110_CHIPSET - Use consistent comparison scheme in nv50_ir_emit_nvc0.cpp Alexandre Courbot (2): nvc0: add GK20A 3D class nvc0: use SM35 ISA with GK20A src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 5 files changed, 21 insertions(+), 8 deletions(-) -- 1.9.3
GK20A is mostly compatible with GK104, but features a new 3D
class. Add it to the relevant header and use it when GK20A is
detected.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
src/gallium/drivers/nouveau/nv_object.xml.h | 1 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h
b/src/gallium/drivers/nouveau/nv_object.xml.h
index 4c93e6564838..0a0e187dc028 100644
--- a/src/gallium/drivers/nouveau/nv_object.xml.h
+++ b/src/gallium/drivers/nouveau/nv_object.xml.h
@@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
#define NVC8_3D_CLASS 0x00009297
#define NVE4_3D_CLASS 0x0000a097
#define NVF0_3D_CLASS 0x0000a197
+#define NVEA_3D_CLASS 0x0000a297
#define GM107_3D_CLASS 0x0000b097
#define NV50_2D_CLASS 0x0000502d
#define NVC0_2D_CLASS 0x0000902d
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index cccfe2bba23d..95e5ef81cd79 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev)
obj_class = NVF0_3D_CLASS;
break;
case 0xe0:
- obj_class = NVE4_3D_CLASS;
+ switch (dev->chipset) {
+ case 0xea:
+ obj_class = NVEA_3D_CLASS;
+ break;
+ default:
+ obj_class = NVE4_3D_CLASS;
+ break;
+ }
break;
case 0xd0:
obj_class = NVC8_3D_CLASS;
--
1.9.3
Alexandre Courbot
2014-May-27 07:03 UTC
[Nouveau] [PATCH v2 2/2] nvc0: use SM35 ISA with GK20A
GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use
the GK110 path when this chip is detected.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +-
.../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++-----
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index bbb89d97932e..f829aac0bcc2 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -91,7 +91,7 @@ struct nv50_ir_prog_symbol
#define NVISA_GF100_CHIPSET_C0 0xc0
#define NVISA_GF100_CHIPSET_D0 0xd0
#define NVISA_GK104_CHIPSET 0xe0
-#define NVISA_GK110_CHIPSET 0xf0
+#define NVISA_GK20A_CHIPSET 0xea
#define NVISA_GM107_CHIPSET 0x110
struct nv50_ir_prog_info
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index b1f76cf80432..f69e6a183e19 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type)
CodeEmitter *
TargetNVC0::getCodeEmitter(Program::Type type)
{
- if (chipset >= NVISA_GK110_CHIPSET)
+ if (chipset >= NVISA_GK20A_CHIPSET)
return createCodeEmitterGK110(type);
return createCodeEmitterNVC0(type);
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 064e7a2c63f9..963b6e47ddfc 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t
*size) const
{
switch (chipset & ~0xf) {
case 0xe0:
- *code = (const uint32_t *)&gk104_builtin_code[0];
- *size = sizeof(gk104_builtin_code);
- break;
+ if (chipset < NVISA_GK20A_CHIPSET) {
+ *code = (const uint32_t *)&gk104_builtin_code[0];
+ *size = sizeof(gk104_builtin_code);
+ break;
+ }
+ /* fall-through for GK20A */
case 0xf0:
case 0x100:
*code = (const uint32_t *)&gk110_builtin_code[0];
@@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const
switch (chipset & ~0xf) {
case 0xe0:
- return gk104_builtin_offsets[builtin];
+ if (chipset < NVISA_GK20A_CHIPSET)
+ return gk104_builtin_offsets[builtin];
+ /* fall-through for GK20A */
case 0xf0:
case 0x100:
return gk110_builtin_offsets[builtin];
@@ -235,7 +240,7 @@ TargetNVC0::getFileSize(DataFile file) const
{
switch (file) {
case FILE_NULL: return 0;
- case FILE_GPR: return (chipset >= NVISA_GK110_CHIPSET) ? 255 :
63;
+ case FILE_GPR: return (chipset >= NVISA_GK20A_CHIPSET) ? 255 :
63;
case FILE_PREDICATE: return 7;
case FILE_FLAGS: return 1;
case FILE_ADDRESS: return 0;
--
1.9.3
On Tue, May 27, 2014 at 3:03 AM, Alexandre Courbot <acourbot at nvidia.com> wrote:> GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use > the GK110 path when this chip is detected. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>> --- > src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- > .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- > 3 files changed, 12 insertions(+), 7 deletions(-) > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > index bbb89d97932e..f829aac0bcc2 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > @@ -91,7 +91,7 @@ struct nv50_ir_prog_symbol > #define NVISA_GF100_CHIPSET_C0 0xc0 > #define NVISA_GF100_CHIPSET_D0 0xd0 > #define NVISA_GK104_CHIPSET 0xe0 > -#define NVISA_GK110_CHIPSET 0xf0 > +#define NVISA_GK20A_CHIPSET 0xea > #define NVISA_GM107_CHIPSET 0x110 > > struct nv50_ir_prog_info > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > index b1f76cf80432..f69e6a183e19 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > @@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) > CodeEmitter * > TargetNVC0::getCodeEmitter(Program::Type type) > { > - if (chipset >= NVISA_GK110_CHIPSET) > + if (chipset >= NVISA_GK20A_CHIPSET) > return createCodeEmitterGK110(type); > return createCodeEmitterNVC0(type); > } > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > index 064e7a2c63f9..963b6e47ddfc 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > @@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const > { > switch (chipset & ~0xf) { > case 0xe0: > - *code = (const uint32_t *)&gk104_builtin_code[0]; > - *size = sizeof(gk104_builtin_code); > - break; > + if (chipset < NVISA_GK20A_CHIPSET) { > + *code = (const uint32_t *)&gk104_builtin_code[0]; > + *size = sizeof(gk104_builtin_code); > + break; > + } > + /* fall-through for GK20A */ > case 0xf0: > case 0x100: > *code = (const uint32_t *)&gk110_builtin_code[0]; > @@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const > > switch (chipset & ~0xf) { > case 0xe0: > - return gk104_builtin_offsets[builtin]; > + if (chipset < NVISA_GK20A_CHIPSET) > + return gk104_builtin_offsets[builtin]; > + /* fall-through for GK20A */ > case 0xf0: > case 0x100: > return gk110_builtin_offsets[builtin]; > @@ -235,7 +240,7 @@ TargetNVC0::getFileSize(DataFile file) const > { > switch (file) { > case FILE_NULL: return 0; > - case FILE_GPR: return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63; > + case FILE_GPR: return (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63; > case FILE_PREDICATE: return 7; > case FILE_FLAGS: return 1; > case FILE_ADDRESS: return 0; > -- > 1.9.3 >
Possibly Parallel Threads
- [PATCH 0/2] nvc0: support for GK20A (Tegra K1)
- [PATCH v2 2/2] nvc0: use SM35 ISA with GK20A
- [PATCH 2/2] nvc0: use SM35 ISA with GK20A
- [PATCH mesa 5/6] nouveau: codegen: Add support for OpenCL global memory buffers
- [PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/