search for: nv50_ir_emit_nvc0

...(SM35). Taking these differences into account is sufficient to successfully render simple off-screen buffers. Alexandre Courbot (2): nvc0: add GK20A 3D class nvc0: use SM35 ISA with GK20A src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 5 files changed, 20 insertions(+), 6 deletions(-) -- 1.9.3

...tly compatible with GK104, but uses the SM35 ISA. Use > the GK110 path when this chip is detected. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- > src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- > 3 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > index bb...

GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h index bbb89d97932e..aab857ee7e4f...

GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h index bbb89d97932e..f829aac0bcc2 1...

...ia Mirkin <imirkin at alum.mit.edu> --- Pretty sure there's nothing wrong with it, but it looks odd in the code. src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++ src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++-- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index 6bb9620..28081fa 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp +++ b/sr...

...s passes the piglit tests. Will test on a NVCX before checking in, in case it's different there. (Although that'd be surprising, given the similarities between the 2 ISAs.) src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 13 +++++++++++-- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 1 + .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 ++++++++-- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 ++- 4 files changed, 22 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/d...

...s/nouveau/codegen/nv50_ir.h | 1 + > .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 31 +++++++++++++++++----- > .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 5 +++- > .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 10 ++++--- > .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 26 +++++++++++++----- > .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 14 +++++++--- > .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5 +++- > .../drivers/nouveau/codegen/nv50_ir_print.cpp | 1 + > .../nouveau/codegen/nv50_ir_target_nv50.cpp | 1...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index dfb093c..e38a3b8 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit...

Hi All, This series implements using double immediates in the nouveau codegen code. This turns the following (nvc0) code: 1: mov u32 $r2 0x00000000 (8) 2: mov u32 $r3 0x3fe00000 (8) 3: add f64 $r0d $r0d $r2d (8) Into: 1: add f64 $r0d $r0d 0.500000 (8) This has been tested with the 2 double shader tests which I just send to the piglet list. On a gk208 (gk110 / SM35)

...--- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 + .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 31 +++++++++++++++++----- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 5 +++- .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 10 ++++--- .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 26 +++++++++++++----- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 14 +++++++--- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5 +++- .../drivers/nouveau/codegen/nv50_ir_print.cpp | 1 + .../nouveau/codegen/nv50_ir_target_nv50.cpp | 1 + .../nouveau/codegen/n...

tgsi_default_instruction_memory / tgsi_build_instruction_memory were returning uninitialized memory for tgsi_instruction_memory.Texture and tgsi_instruction_memory.Format. Note 0 means not set, and thus is a correct default initializer for these. Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory") Cc: Nicolai Hähnle <nicolai.haehnle at amd.com>

...+- > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 10 > +++++----- > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 6 +++--- > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 10 > +++++----- > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 12 > ++++++------ > src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 8 ++++---- > .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 > +++++----- > src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8 ++++---- > src/gallium/d...

Some shaders appear to extract bits using shift/and combos. Detect (some) of those and convert to EXTBF instead. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 66 +++++++++++++++------- 1 file changed, 46 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

...n/nv50_ir.h | 1 + >> .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 31 +++++++++++++++++----- >> .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 5 +++- >> .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 10 ++++--- >> .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 26 +++++++++++++----- >> .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 14 +++++++--- >> .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5 +++- >> .../drivers/nouveau/codegen/nv50_ir_print.cpp | 1 + >> .../nouveau/codegen/nv50_ir_target_nv50....

...nv50_ir.h | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 10 +++++----- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 6 +++--- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 10 +++++----- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 12 ++++++------ src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 8 ++++---- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 +++++----- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8 ++++---- src/gallium/drivers/nouveau/codegen/nv50_ir...

...ivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 10 >> +++++----- >> src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 6 +++--- >> src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 10 >> +++++----- >> src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 12 >> ++++++------ >> src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 8 ++++---- >> .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 >> +++++----- >> src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8 ++++-...

...ople.freedesktop.org/~imirkin/tess_shaders_quads.txt My suspicion is that we're doing something wrong with the sched codes. We have an elaborate calculator, but... perhaps not elaborate enough? You can see it here: http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp#n2574 The reason I think it's an error in sched codes is due to the TRAP memory location that I see -- could well be some "stale" value in the register and the value from S2R or VILD doesn't make it in there in time before the ALD reads it. If you should like to try this you...

...>> >> My suspicion is that we're doing something wrong with the sched codes. >> We have an elaborate calculator, but... perhaps not elaborate enough? >> You can see it here: >> >> http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp#n2574 >> >> The reason I think it's an error in sched codes is due to the TRAP >> memory location that I see -- could well be some "stale" value in the >> register and the value from S2R or VILD doesn't make it in there in >> time before the ALD r...

https://bugs.freedesktop.org/show_bug.cgi?id=90348 Bug ID: 90348 Summary: Spilling failure of b96 merged value Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau Assignee: nouveau at