Christoph Bumiller
2013-Dec-25 17:00 UTC
[Nouveau] [PATCH] drm/nve4: fix size of POLY2ESETUP buffer
This fixes write faults from GPCCLIENT 5 in geometry shader tests. For now this is just a guess from a single mmio trace, it looks like 8 large pages are being used, i.e. one per TPC. Can we just ask NV for the correct sizes ? --- drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c index e2de73e..ff0960f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c @@ -813,7 +813,7 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); - mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); + mmio_data(priv->gpc_nr << 17, 0x1000, NV_MEM_ACCESS_RW); mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x408010, 0x80000000, 0, 0); mmio_list(0x419004, 0x00000000, 8, 1); -- 1.8.1.5
Apparently Analagous Threads
- [PATCH] drm/nve4: fix size of POLY2ESETUP buffer (s/gpc_nr/tpc_total)
- [RFC PATCH] drm/gk208/gr: adjust a couple of init values
- [PATCH 10/12] drm/nouveau/graph: add GK20A support
- [PATCH 10/12] drm/nouveau/graph: add GK20A support
- [PATCH] drm/gk208/gr: add missing registers to grctx init