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This fixes write faults from GPCCLIENT 5 in geometry shader tests. For now this is just a guess from a single mmio trace, it looks like 8 large pages are being used, i.e. one per TPC. Can we just ask NV for the correct sizes ? --- drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-...

This fixes write faults from GPCCLIENT 5 in geometry shader tests. For now this is just a guess from a single mmio trace, it looks like 8 large pages are being used, i.e. one per TPC. Can we just ask NV for the correct sizes ? --- drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-...

This is an initial series of patches to improve channel recovery on Turing GPUs with the goal of improving reliability enough to eventually enable SVM for Turing. It's likely follow up patches will be required to fully address problems with less trivial workloads than what I have been able to test thus far. This series primarily addresses a number of hardware changes to interrupt layout and

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot: