llvm dev - Jul 2019 - Manipulating global address inside GlobalAddress SDNode in (RISCV) LLVM backend

Hello,

Brief background: We are trying to support 64 bit pointers in RISCV 32 bit
backend
http://lists.llvm.org/pipermail/llvm-dev/2019-June/132805.html

To pass the legalizer we plan to break the 64 bit GlobalAddress into 32 bit
GlobalAddress having the other 32 bit glued to the node. We could not find
a direct way to convert the 64 bit GlobalAddress Node into a 32 bit node.

For a GlobalAddress node say i64 = GlobalAddress<0xHighLow> we want to
convert it into i32 = GlobalAddress<0xLow>.

[The below part is in reference with the RISCV LLVM backend]
If there is no direct way to do this, we plan to fall back on a backup plan
to convert the GlobalAddress node into the required LUI and ADDI pair but
that would require the addition of two new target flag in RISCVII
namespace.

- Reshabh
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On Tue, 9 Jul 2019 at 14:49, Reshabh Sharma via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> For a GlobalAddress node say i64 = GlobalAddress<0xHighLow> we want
to convert it into i32 = GlobalAddress<0xLow>.
I think you'd have to convert it into a custom RISCVGlobalAddressLow
and RISCVGlobalAddressHigh pair because the type of GlobalAddress is
fixed to pointer type in TargetSelectionDAG.td (that's not 100% set in
stone, but I wouldn't violate it lightly). And that might well be
functionally equivalent to making an LUI/ADDI pair directly.
> If there is no direct way to do this, we plan to fall back on a backup plan
to convert the GlobalAddress node into the required LUI and ADDI pair but that
would require the addition of two new target flag in RISCVII namespace.
I don't think there's a real shortage of those, but I confess I'm
not
sure why that's related. You'd need a representation for the LUI and
ADDI after instruction selection anyway.

Cheers.

Tim.

>
> I don't think there's a real shortage of those, but I confess
I'm not
> sure why that's related. You'd need a representation for the LUI
and
> ADDI after instruction selection anyway.

Yeah at the end we need a representation for LUI and ADDI. We were trying
to break the 64 bit address from GlobalAddress node into two i32 register.
We will add custom load/store which will generate the address using values
from two registers. We thought LUI and ADDI pair will be good to store the
values in a i32 register.  If we could transform GlobalAddress<0xHighLow>
directly to GlobalAddress<0xLow>, we could use the present RISCVII::MO_HI
and MO_LO as they only exact the 32 high bits. What do you think?
Many thanks for your reply :)

On Tue, Jul 9, 2019 at 9:41 PM Tim Northover <t.p.northover at gmail.com>
wrote:
> On Tue, 9 Jul 2019 at 14:49, Reshabh Sharma via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> > For a GlobalAddress node say i64 = GlobalAddress<0xHighLow> we
want to
> convert it into i32 = GlobalAddress<0xLow>.
>
> I think you'd have to convert it into a custom RISCVGlobalAddressLow
> and RISCVGlobalAddressHigh pair because the type of GlobalAddress is
> fixed to pointer type in TargetSelectionDAG.td (that's not 100% set in
> stone, but I wouldn't violate it lightly). And that might well be
> functionally equivalent to making an LUI/ADDI pair directly.
>
> > If there is no direct way to do this, we plan to fall back on a backup
> plan to convert the GlobalAddress node into the required LUI and ADDI pair
> but that would require the addition of two new target flag in RISCVII
> namespace.
>
> I don't think there's a real shortage of those, but I confess
I'm not
> sure why that's related. You'd need a representation for the LUI
and
> ADDI after instruction selection anyway.
>
> Cheers.
>
> Tim.
>
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