llvm dev - Mar 2018 - Live Interval Analysis and pipelining.

Hi,

I'm writing a backend for a proprietary microcontroller.
I'm facing a limitation related to Live Interval Analysis.
Some FPU instructions, most notably the FDIV, requires a few cycles to complete.
There is a pipeline and, during the execution of the FDIV, others instructions
could be executed in parallel, provided they don't use the same registers.
This pipeline has been modeled for the instruction scheduling through
SchedMachineModel and ProcessorItineraries in .td file.
My problem is that the Live Interval Analysis seems to be over optimistic. It
consider that the interval is closed when the FPU instruction start, not when it
is completed.
With such analysis it reallocate a physical register to early, while still used
by the FPU instruction, which compromises the FPU result.

Is there a mechanism (.td scheduling model or C++ hook) to extend the live
analysis range in order to cover the pipeline execution?

Thanks in advance,          Dominique Torette.







[http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg]

Dominique Torette
System Architect
Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur
Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20
www.spacebel.be<http://www.spacebel.be/>



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Hi,
Live interval analysis represents a certain model of data flow, not the 
actual hardware behavior.  The model is such that the last register use 
(for a given definition) ends the live segment for that register.
Dealing with the hardware behavior is left to the schedulers. In 
particular, targets can provide their of hazard recognizers to aid the 
scheduling (see the ScheduleHazardRecognizer class).

-Krzysztof

On 3/27/2018 9:43 AM, Dominique Torette via llvm-dev
wrote:
> Hi,
> 
> I’m writing a backend for a proprietary microcontroller.
> 
> I’m facing a limitation related to Live Interval Analysis.
> 
> Some FPU instructions, most notably the FDIV, requires a few cycles to 
> complete.
> 
> There is a pipeline and, during the execution of the FDIV, others 
> instructions could be executed in parallel, provided they don’t use the 
> same registers.
> 
> This pipeline has been modeled for the instruction scheduling through 
> SchedMachineModel and ProcessorItineraries in .td file.
> 
> My problem is that the Live Interval Analysis seems to be over 
> optimistic. It consider that the interval is closed when the FPU 
> instruction start, not when it is completed.
> 
> With such analysis it reallocate a physical register to early, while 
> still used by the FPU instruction, which compromises the FPU result.
> 
> Is there a mechanism (.td scheduling model or C++ hook) to extend the 
> live analysis range in order to cover the pipeline execution?
> 
> Thanks in advance,          Dominique Torette.
> 
> 
> 
> 
> 
> 
> 
> http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg
> 
> *Dominique Torette*
> System Architect
> Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur
> Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20
> www.spacebel.be <http://www.spacebel.be/>
> 
> 
>
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> 
> SPACEBEL denies all liability for incomplete, improper, inaccurate, 
> intercepted, (partly) destroyed, lost and/or belated transmission of the 
> current information given that unencrypted electronic transmission 
> cannot currently be guaranteed to be secure or error free.
> Upon request or in conformity with formal, contractual agreements, an 
> originally signed hard copy will be sent to you to confirm the 
> information contained in this E-mail.
> 
> SPACEBEL denies all liability where E-mail is used for private use.
> 
> SPACEBEL cannot be held responsible for possible viruses that might 
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