search for: processoritinerari

I'd appreciate some help in figuring out how to determine which InstrItinClass an instruction belongs to. For example, an InstrItinClass is defined in Schedule.td as: def FOO : InstrItinClass; Which is then used to build an InstrItinData in ProcessorItineraries and to specify the class of a particular instruction. I'd like to find out from a given instruction which class it belongs to, "FOO" or any other. TIA -- Evandro Menezes Austin, TX emenezes at codeaurora.org Qualcomm Innovation Center, Inc is a member of Code Aur...

...es wrote: > I'd appreciate some help in figuring out how to determine which > InstrItinClass an instruction belongs to. > > For example, an InstrItinClass is defined in Schedule.td as: > > def FOO : InstrItinClass; > > Which is then used to build an InstrItinData in ProcessorItineraries and > to specify the class of a particular instruction. > > I'd like to find out from a given instruction which class it belongs to, > "FOO" or any other. > > TIA > > -- > Evandro Menezes Austin, TX emenezes at codeaurora.org > Qualc...

...ora Forum, hosted by The Linux Foundation *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On Behalf Of *Jonas Paulsson *Sent:* Monday, February 11, 2013 11:16 AM *To:* llvmdev at cs.uiuc.edu *Subject:* [LLVMdev] DFAPacketizer Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express...

...inheriting from AsI1_bin_irs (shown below) which, in turn, associates Sched<[WriteALU, ReadALU]> with the instruction. defm AND : AsI1_bin_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; In my mind, we have latencies defined from the ProcessorItineraries, latencies defined in the SchedReadWrite representation which are mapped through SchedAlias to the ANDri and, in the end, a mapping (or overriding?) of the latencies in the Itineraries by the processor-specific SchedWrites, through the InstRW? Can someone share some light on what scheduling/lant...

...using Y-bundles would be more efficient. Too bad, Y-bundles can't contain arbitrary instructions. So, there are 5 virtual pipelines: X0, X1, Y0, Y1, Y2. I can define that which pipelines can be used to perform an instruction. On the other hand, AFAIK one subtarget can be matched only with one ProcessorItineraries and all its FuncUnits may be used in each bundle. Thus, I can't constraint bundles to use either X0, X1 or Y0, Y1, Y2, and never mix them. Is there a way to define two types of bundles using the current capabilities of TableGen and CodeGen? Or had I better use only X-bundles for now? Thanks...

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>, InstrItinData<LD, [InstrStage<1, [Slot0, Slot1]>]>, // <-- This itinerary class describes load instructions InstrItinData<BR, [...

...ably the FDIV, requires a few cycles to complete. There is a pipeline and, during the execution of the FDIV, others instructions could be executed in parallel, provided they don't use the same registers. This pipeline has been modeled for the instruction scheduling through SchedMachineModel and ProcessorItineraries in .td file. My problem is that the Live Interval Analysis seems to be over optimistic. It consider that the interval is closed when the FPU instruction start, not when it is completed. With such analysis it reallocate a physical register to early, while still used by the FPU instruction, which c...

...edu>[mailto:llvmdev-bounces at cs.uiuc.edu] > *On Behalf Of *Jonas Paulsson > *Sent:* Monday, February 11, 2013 11:16 AM > *To:* llvmdev at cs.uiuc.edu <mailto:llvmdev at cs.uiuc.edu> > *Subject:* [LLVMdev] DFAPacketizer > > Hi, > > I am having problems writing the ProcessorItineraries list. As > instructions on my VLIW target have varying size I want to model both > cpu units and bundle bits as FUs. The following does not work, to my > surprise: > > InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, > > InstrStage<1, [ALU1,...

...clude/llvm/Target/TargetSchedule.td": def NoSchedModel : SchedMachineModel { let NoModel = 1; let CompleteModel = 0; } ... which is made the default model in code generated from this snippet of "llvm/include/llvm/Target/Target.td": class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { [...] SchedMachineModel SchedModel = NoSchedModel; So, all in all, given the current structure of this part of LLVM, there seems to be no way to make a particular ISA have defaults different than the global defaults, and in AArch64 I can`t s...

....uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Jonas Paulsson Sent: Monday, February 11, 2013 11:16 AM To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu> Subject: [LLVMdev] DFAPacketizer Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]&...

...ies = CortexA8Itineraries; } If you don't actually have any itineraries defined in you target's Schedule.td files, you need to define some dummy itinerary with at least one entry. Something like this may work (I haven't tried it). def IIC_Default : InstrItinClass; def MyItineraries : ProcessorItineraries<[ InstrItinData<IIC_Default, [], []> ]>; 3) The new style of machine model. Here, you don't use any hooks above the machine model. Instead you define all possible instruction latencies and resources in your .td. For a particular opcode, the model allows selecting the set of re...

....uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Jonas Paulsson Sent: Monday, February 11, 2013 11:16 AM To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu> Subject: [LLVMdev] DFAPacketizer Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]&...

Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]&...

...rary class data for the PPC 440 > processor. >>>>>> +// >>>>>> > +//===---------------------------------------------------------------------- > ===// >>>>>> + >>>>>> + >>>>>> +def PPC440Itineraries : ProcessorItineraries< >>>>>> + [IFTH1, IFTH2, PDCD1, PDCD2, DISS1, DISS2, FRACC, >>>>>> + IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, > LWB, >>>>>> + FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold], >>>>>>...

...: InstrItinClass; >> def ST : InstrItinClass; >> def S : InstrItinClass; >> +def SYS : InstrItinClass; >> +def MARKER : InstrItinClass; >> def PSEUDO : InstrItinClass; >> >> - >> def HexagonItineraries : >> - ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [ >> - InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, >> - InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>, >> - InstrItinData<CR , [InstrStage<1, [SUNIT]&g...