search for: spacebel

Displaying 20 results from an estimated 21 matches for "spacebel".

2018 Mar 29
4
Mapping virtual registers to physical registers
...ang-up in an infinite loop in procedure computeVirtRegs(); of pass LiveIntervals::runOnMachineFunction. In other targets, I've seen an example with a setIsDef(true) for such physically mapped register. Is there something missing in my code (register other setting,...) ? [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2017 Jul 27
2
Are there some strong naming conventions in TableGen?
...definition based on a naming convention related to the "imm" string. Are such naming conventions quite common for TableGen target descition input file? Do I have to rename IMM16Operand into something like imm16Operand? Thanks in advance. Dominique Torette. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 Mar 27
1
Live Interval Analysis and pipelining.
...gister to early, while still used by the FPU instruction, which compromises the FPU result. Is there a mechanism (.td scheduling model or C++ hook) to extend the live analysis range in order to cover the pipeline execution? Thanks in advance, Dominique Torette. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2017 Sep 20
1
Store lowering -> Cannot select FrameIndex.
...o lower the FrameIndex node !!! This failed... ISEL: Starting pattern match on root node: t2: i16 = FrameIndex<0> Initial Opcode index to 0 Match failed at index 0 LLVM ERROR: Cannot select: t2: i16 = FrameIndex<0> How to discard this FrameIndex<0> ? [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 Mar 30
0
Mapping virtual registers to physical registers
...hang-up in an infinite loop in procedure computeVirtRegs(); of pass LiveIntervals::runOnMachineFunction. In other targets, I've seen an example with a setIsDef(true) for such physically mapped register. Is there something missing in my code (register other setting,...) ? [http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> --------...
2018 May 04
2
How to constraint instructions reordering from patterns?
...ces have no glue, so later during Instruction Scheduling/SelectionDiag linearization the instructions are moved out of valid context. Is there some Instruction flags or others features that could delimit the reordering could cross some limit? TIA, Dominique Torette [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 Apr 03
1
Mapping virtual registers to physical registers
...of pass > LiveIntervals::runOnMachineFunction. > > In other targets, I’ve seen an example with a setIsDef(true) for such > physically mapped register. Is there something missing in my code > (register other setting,…) ? > > > > > > > http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1. > jpg > > *Dominique Torette* > System Architect > Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur > Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be > <http:/...
2017 Jul 24
2
How to lower a 'Store' node using the list<dag> pattern.
...on matchers tables, I got the following assertion. This assertion start to occur when the pattern is introduced on the MOVSUTO_SU_rr. How to avoid such assertion? What is a concrete type? According to the definition of SURegisterOperand, these are 16 bits signed integer. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 Apr 02
0
Mapping virtual registers to physical registers
...of pass > LiveIntervals::runOnMachineFunction. > > In other targets, I’ve seen an example with a setIsDef(true) for such > physically mapped register. Is there something missing in my code > (register other setting,…) ? > > > > > > > http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg > > *Dominique Torette* > System Architect > Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur > Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 > www.spacebel.be <http://www....
2018 Apr 10
1
How to finalize instruction lowering after register allocation.
...lassAB into the _two overlapping physical sub-registers_ ! Has someone an idea to properly lowering and allocating registers to BUILD_VECTOR, considering my SIMD registers definition and my instructions set? Thanks in advance, comments are welcome. Dominique Torette. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2014 Mar 06
4
[LLVMdev] llvm-mc and endianess.
...47;genobj.html) that defines two different targets and performs the byte swapping as part of the 'EmitInstruction'. Is it the right way? Could somebody confirm my understanding and give me some tips about endianess in llvm-mc? Thanks, Dominique T. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 May 04
2
How to constraint instructions reordering from patterns?
...> Scheduling/SelectionDiag linearization the instructions are moved out of > valid context. > > Is there some Instruction flags or others features that could delimit > the reordering could cross some limit? > > TIA,        Dominique Torette > > http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg > > *Dominique Torette* > System Architect > Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur > Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 > www.spacebel.be <http://www....
2018 May 04
0
How to constraint instructions reordering from patterns?
...> Scheduling/SelectionDiag linearization the instructions are moved out > of valid context. > > Is there some Instruction flags or others features that could delimit > the reordering could cross some limit? > > TIA,        Dominique Torette > > http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1. > jpg > > *Dominique Torette* > System Architect > Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur > Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be > <http:/...
2018 Sep 20
2
Errononous scheduling of COPY instruction.
...: 0 # succs left : 1 # rdefs left : 0 Latency : 0 Depth : 0 Height : 25 Successors: SU(21): Data Latency=0 Reg=%6 Pressure Diff : FPUaOffsetClass -1 FPUabOffsetClass -1 Single Issue : false; [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...%vreg8 FPUaOffsetClass:%vreg4,%vreg7 144B %FA_ROFF0<def> = COPY %vreg8; FPUaROUTADDRegisterClass:%vreg8 176B MOVSUTO_SU_os_rpc %SU_ROFF0<kill>, %RPC<imp-def,dead> 192B NOP # End machine code for function addproddivConst. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...dMI(*MBB, MI, Loc, TII->get(HOpcode)) .add(operand0) .add(operand1); MI.eraseFromParent(); return MBB; } Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be ------------------------------------------------------------------------------ E-MAIL DISCLAIMER The present message may contain confidential and/or legally privileged information. If you are not the intended addressee and in case of a transmission error, please notify the sender imm...
2017 Sep 27
0
PEI::replaceFrameIndices() endless loop
...perand, we need to // use that target machine register info object to eliminate // it. TRI.eliminateFrameIndex(MI, SPAdj, i, FrameIndexVirtualScavenging ? nullptr : RS); Regards, Dominique Torette. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 May 04
0
How to constraint instructions reordering from patterns?
...nces have no glue, so later during Instruction Scheduling/SelectionDiag linearization the instructions are moved out of valid context. Is there some Instruction flags or others features that could delimit the reordering could cross some limit? TIA, Dominique Torette [http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> --------...
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
...Class:%vreg9 FPUabRegisterClass:%vreg7 %vreg8<def> = FMUL_AB_oo %vreg0, %vreg9<kill>, %RFLAGA<imp-def,dead>, %RFLAGB<imp-def,dead>, %RSPA<imp-use>, %RSPB<imp-use>; FPUabROUTMULRegisterClass:%vreg8 FPUabOffsetClass:%vreg0,%vreg9 [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...
2018 Jun 20
2
Node deletion during DAG Combination ?
...32,ch = LOAD_AB_o TargetFrameIndex:i16<0>, t57:1 t61: i32,ch = LOAD_A_i TargetConstant:i32<24575>, t58:1 t72: f32 = LOAD_A_o TargetFrameIndex:i16<0>, t57:1 t62: ch = WRITEAPB_A_oo t61, t72, t58:1 [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------...