search for: torette

Displaying 20 results from an estimated 21 matches for "torette".

2017 Jul 27
2
Are there some strong naming conventions in TableGen?
...code seems to retrieve some Node definition based on a naming convention related to the "imm" string. Are such naming conventions quite common for TableGen target descition input file? Do I have to rename IMM16Operand into something like imm16Operand? Thanks in advance. Dominique Torette. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------------...
2018 Mar 27
1
Live Interval Analysis and pipelining.
...analysis it reallocate a physical register to early, while still used by the FPU instruction, which compromises the FPU result. Is there a mechanism (.td scheduling model or C++ hook) to extend the live analysis range in order to cover the pipeline execution? Thanks in advance, Dominique Torette. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ---------------...
2014 Mar 06
4
[LLVMdev] llvm-mc and endianess.
...s the byte swapping as part of the 'EmitInstruction'. Is it the right way? Could somebody confirm my understanding and give me some tips about endianess in llvm-mc? Thanks, Dominique T. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------------------------------------------------------------------------ E-MAIL DISCLAIMER The present me...
2018 Mar 30
0
Mapping virtual registers to physical registers
...qrXKzD2DtrP8F80Uyc48XqNNjuzvmT7TK7cDvvzhGtUvS4WXZfr-70e3-6fpQa4k&u=https%3A%2F%2Fllvm.org%2Fdocs%2FCodeGenerator.html%23mapping-virtual-registers-to-physical-registers> still valid ? Are there other options to enforce the mapping of virtual registers to physical ones ? TIA, Dominique Torette. From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Dominique Torette via llvm-dev Sent: jeudi 29 mars 2018 15:48 To: llvm-dev at lists.llvm.org Subject: [llvm-dev] Mapping virtual registers to physical registers Hi, In the context of MachineCode custom inserter, I'm try...
2017 Jul 24
2
How to lower a 'Store' node using the list<dag> pattern.
...ion start to occur when the pattern is introduced on the MOVSUTO_SU_rr. How to avoid such assertion? What is a concrete type? According to the definition of SURegisterOperand, these are 16 bits signed integer. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------------------------------------------------------------------------ E-MAIL DISCLAIMER The present me...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...ly includes FA_ROUTMUL). So spill out need to be inserted where I tried to avoid it by inserting the COPY. :-/ This 'handleMove' is generated by LiveIntervalAnalysis, but I don't understand why it is generated and how to avoid this counterproductive optimization. TIA, Dominique Torette. # *** IR Dump After MachineFunction Printer ***: # Machine code for function addproddivConst: Post SSA Function Live Ins: %FA_ROFF1 in %vreg0 0B BB#0: derived from LLVM BB %entry Live Ins: %FA_ROFF1 16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0 32B...
2018 Apr 10
1
How to finalize instruction lowering after register allocation.
...on) _one Virtual Register_ of RegClassAB into the _two overlapping physical sub-registers_ ! Has someone an idea to properly lowering and allocating registers to BUILD_VECTOR, considering my SIMD registers definition and my instructions set? Thanks in advance, comments are welcome. Dominique Torette. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> -----------------...
2018 Mar 29
4
Mapping virtual registers to physical registers
...pass LiveIntervals::runOnMachineFunction. In other targets, I've seen an example with a setIsDef(true) for such physically mapped register. Is there something missing in my code (register other setting,...) ? [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------------------------------------------------------------------------ E-MAIL DISCLAIMER The present me...
2018 Sep 20
2
Errononous scheduling of COPY instruction.
...Latency : 0 Depth : 0 Height : 25 Successors: SU(21): Data Latency=0 Reg=%6 Pressure Diff : FPUaOffsetClass -1 FPUabOffsetClass -1 Single Issue : false; [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------------------------------------------------------------------------ E-MAIL DISCLAIMER The present me...
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...rand operand1 = MI.getOperand(1); BuildMI(*MBB, MI, Loc, TII->get(LOpcode)) .add(operand0) .add(operand1); BuildMI(*MBB, MI, Loc, TII->get(HOpcode)) .add(operand0) .add(operand1); MI.eraseFromParent(); return MBB; } Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be ------------------------------------------------------------------------------ E-MAIL DISCLAIMER The present message may contain confidentia...
2018 May 04
2
How to constraint instructions reordering from patterns?
...SDNodes/Instructions. Such sequences have no glue, so later during Instruction Scheduling/SelectionDiag linearization the instructions are moved out of valid context. Is there some Instruction flags or others features that could delimit the reordering could cross some limit? TIA, Dominique Torette [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ---------------------...
2018 May 04
2
How to constraint instructions reordering from patterns?
The DAG dumping will try to print some of the nodes "inline" (i.e. where they are used) to make the output more readable, so the dump of the DAG may not strictly reflect the node ordering. -Krzysztof On 5/4/2018 8:18 AM, Dominique Torette via llvm-dev wrote: > Here is a last example to illustrate my concern. > > The problem is about the lowering of node t13. > > Initial selection DAG: BB#0 '_start:entry' > > SelectionDAG has 44 nodes: > >   t11: i16 = Constant<0> > >             ...
2018 Apr 12
0
How to specify the RegisterClass of an IMPLICIT_DEF?
On 4/12/2018 8:01 AM, Dominique Torette via llvm-dev wrote: > > But there is one small issue in the inference of RegisterClass of the > implicitly defined register. > > As shown below, the %vreg6<def> is implicitly defined as FPUabRegisterClass. > > This register class accepts the v2f32 type, but for others...
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
...t; = FMUL_AB_oo %vreg0, %vreg9<kill>, %RFLAGA<imp-def,dead>, %RFLAGB<imp-def,dead>, %RSPA<imp-use>, %RSPB<imp-use>; FPUabROUTMULRegisterClass:%vreg8 FPUabOffsetClass:%vreg0,%vreg9 [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------------------------------------------------------------------------ E-MAIL DISCLAIMER The present me...
2018 May 04
0
How to constraint instructions reordering from patterns?
...w to constraint instructions reordering from patterns? The DAG dumping will try to print some of the nodes "inline" (i.e. where they are used) to make the output more readable, so the dump of the DAG may not strictly reflect the node ordering. -Krzysztof On 5/4/2018 8:18 AM, Dominique Torette via llvm-dev wrote: > Here is a last example to illustrate my concern. > > The problem is about the lowering of node t13. > > Initial selection DAG: BB#0 '_start:entry' > > SelectionDAG has 44 nodes: > >   t11: i16 = Constant<0> > >             ...
2018 May 04
0
How to constraint instructions reordering from patterns?
...37, t37:1 t41: ch,glue = CALLSEQ_END TargetConstant:i16<4>, TargetConstant:i16<0>, t39, t39:1 t42: f32,ch,glue = COPY_TO_CALLER_A TargetFrameIndex:i16<0>, t41, t41:1 t43: ch = RET_FLAG t42:1 From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Dominique Torette via llvm-dev Sent: vendredi 4 mai 2018 12:43 To: llvm-dev at lists.llvm.org Subject: [llvm-dev] How to constraint instructions reordering from patterns? Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how t...
2017 Sep 20
1
Store lowering -> Cannot select FrameIndex.
...pattern match on root node: t2: i16 = FrameIndex<0> Initial Opcode index to 0 Match failed at index 0 LLVM ERROR: Cannot select: t2: i16 = FrameIndex<0> How to discard this FrameIndex<0> ? [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> ------------------------------------------------------------------------------ E-MAIL DISCLAIMER The present me...
2017 Sep 27
0
PEI::replaceFrameIndices() endless loop
...// If this instruction has a FrameIndex operand, we need to // use that target machine register info object to eliminate // it. TRI.eliminateFrameIndex(MI, SPAdj, i, FrameIndexVirtualScavenging ? nullptr : RS); Regards, Dominique Torette. [http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg] Dominique Torette System Architect Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 www.spacebel.be<http://www.spacebel.be/> -------------------...
2018 Apr 03
1
Mapping virtual registers to physical registers
...have explicit subregisters in machine operands. Calling setIsDef on an existing operand is not a good practice. If you want to make significant changes to an instruction, it's usually better to build a new one and remove the old one. Hope this helps, -Krzysztof On 3/29/2018 8:47 AM, Dominique Torette via llvm-dev wrote: > Hi, > > In the context of MachineCode custom inserter, I’m trying to enforce > the mapping of virtual register to a physical one. > > According to the documentation > https://clicktime.symantec.com/a/1/qLQUsovqBxYmtEpyYF4Fx_S26wH68VrDlLt > fEAs6I_0=?...
2018 Apr 02
0
Mapping virtual registers to physical registers
...e explicit subregisters in machine operands. Calling setIsDef on an existing operand is not a good practice. If you want to make significant changes to an instruction, it's usually better to build a new one and remove the old one. Hope this helps, -Krzysztof On 3/29/2018 8:47 AM, Dominique Torette via llvm-dev wrote: > Hi, > > In the context of MachineCode custom inserter, I’m trying to enforce the > mapping of virtual register to a physical one. > > According to the documentation > https://llvm.org/docs/CodeGenerator.html#mapping-virtual-registers-to-physical-regist...