hameeza ahmed via llvm-dev
2017-Jun-23 01:57 UTC
[llvm-dev] AVX-512 foldable instructions Pattern Matching VMOVDQU32Zm
Hello,
I am trying to understand the vectorized llvm instruction selection
(pattern matching). there i found how
store<ST64[bitcast (i32* getelementptr inbounds ([34 x i32], [34 x i32]*
@a, i64 0, i64 16) to <16 x i32>*)](align=16)(tbaa=<0x2c96d88>)>
is mapped
to
VMOVDQU32Zmr<Mem:ST64[bitcast (i32* getelementptr inbounds ([34 x i32], [34
x i32]* @a, i64 0, i64 16) to <16 x
i32>*)](align=16)(tbaa=<0x2c96d88>)>
Register:i64 %RIP, TargetConstant:i8<1>, Register:i64 %noreg,
TargetGlobalAddress:i32<[34 x i32]* @a> + 64, Register:i32 %noreg, t16,
t18
but when i searched VMOVDQU32Zm instruction i didnt find its definition in
.td file rather its mentioned in x86instrinfo.cpp still not defined rather
it says AVX-512 foldable instructions
it is just called via .inc file.
{ X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Please clarify the concept of pattern matching for such instructions. what
are foldable instructions?
Thank You
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20170623/62e0ecef/attachment.html>
Friedman, Eli via llvm-dev
2017-Jun-23 02:14 UTC
[llvm-dev] AVX-512 foldable instructions Pattern Matching VMOVDQU32Zm
On 6/22/2017 6:57 PM, hameeza ahmed via llvm-dev wrote:> but when i searched VMOVDQU32Zm instruction i didnt find its > definition in .td fileLook for "defm VMOVDQU32". See also http://llvm.org/docs/TableGen/LangIntro.html#multiclass-definitions-and-instances -Eli -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project