Johnson, Nicholas Paul via llvm-dev
2017-Jun-05 21:18 UTC
[llvm-dev] reg alloc bug? "Different value live out of predecessor"
I'm experiencing a few related assert-failures in the register allocator. Unfortunately, I can only reproduce these in my out-of-tree backend :( I'm looking for advice how to debug these failures. -verify-regalloc exposes the error. It occurs when RAGreedy::splitAroundRegion calls MF->verify("After splitting live range around region"). The error report says "Different value live out of predecessor." I believe that the error pertains to this to %vreg190 defined below---a particularly ugly IMPLICIT_DEF of a lower lane of a 2xi32 vector register. Any tips would be appreciated Nick Johnson D. E. Shaw Research ... 4144B BB#47: derived from LLVM BB %bb158 Predecessors according to CFG: BB#46 4160B %vreg19<def> = INSTR_LA_S__I <ga:@baz.607>; ScalarRegs:%vreg19 4176B %vreg190:sub_32_1<def,read-undef> = IMPLICIT_DEF; PairRegs:%vreg190 Successors according to CFG: BB#48(?%) 4208B BB#48: derived from LLVM BB %bb162 Predecessors according to CFG: BB#46 BB#47 4256B INSTR_SW__S_I_S %vreg166, %R0_0, 782064; mem:ST4[undef](tbaa=!8) ScalarRegs:%vreg166 4328B %vreg176<def> = INSTR_LW_S__I_S <fi#2>, 0; mem:LD4[FixedStack2] ScalarRegs:%vreg176 4332B %vreg191<def> = COPY %vreg190; PairRegs:%vreg191,%vreg190 4336B INSTR_BNE__S_I_I_I__S_U__TARGET_MUL_4 %R0_0, 0, <BB#11>, 0 4352B INSTR_J__I_I__U__TARGET_MUL_4 <BB#53>, 0 Successors according to CFG: BB#53(0x7ffff800 / 0x80000000 = 100.00%) BB#11(0x00000800 / 0x80000000 = 0.00%) ... *** Bad machine code: Different value live out of predecessor *** - function: ham.928 - basic block: BB#47 bb158 (0x471ee70) [4144B;4208B) - liverange: [2280r,3424B:0)[3440B,4144B:0)[4208B,4332r:0) 0 at 2280r - v. register: %vreg190 - lanemask: 00000001 At which point MachineVerifier::verifyLiveRangeSegment() segfaults as it appempts to dereference PVNI->id with null PVNI. Valno #4294967295 live out of BB#47 at 4208B Valno #0 live into BB#48 at 4208B LLVM ERROR: Found 1 machine code errors.